Rambus Inc Patent Portfolio Statistics

Rambus Inc

Rambus Inc`s Profile

This article summarizes the perfomance of the assignee in the recent years. The overall statistics for this portfolio help to analyze the areas where the assignee is performing well. The filing trend, perfomance across the tech centers and the perfomance of the recent applications has been mentioned below. All the stats are calculated based on the perfomance in USPTO.

How does the overall patent portfolio of Rambus Inc look like?

Total Applications:	339
Granted Patents:	322
Grant Index	97.28 %
Abandoned/Rejected Applications:	9 (2.72%)
In-Process Applications:	8
Average Grant Time:	1.75 Years
Average Office Actions:	1.19

Which Technology Area Rambus Inc is filing most patents in? (Last 10 years)

Art Unit	Definition	Total Applications
2827	Semiconductors/Memory	32
2632	Digital and Optical Communications	23
2631	Digital and Optical Communications	20
2824	Semiconductors/Memory	18
2842	Electrical Circuits and Systems	18

How many patents are Rambus Inc filing every year?

Year	Total Applications
2022	0*
2021	0*
2020	0
2019	75
2018	115

*The drop in the number of applications filed in last two years compared to previous years is because applications can take up to 18 months to get published

Recently filed patent applications of Rambus Inc in USPTO?

Publication number: US20220027093A1

Abstract:
An integrated-circuit memory component receives, as part of respective first and second memory read transactions, a first column access command that identifies a first volume of data and a second column read command that identifies a second volume of data, the second volume of data being constituted by not more than half as many data bits as the first volume of data. In response to receiving the first column access command, the integrated-circuit memory component transmits the first volume of data as N parallel bit-serial data signals over N external signaling links. In response to receiving the second column access command, the integrated-circuit memory component transmits the second volume of data as M parallel bit- serial data signals over M of the N external signaling links, where M is less than N.

Publication date: 2022-01-27
Applicant: Rambus Inc
Inventors: A Frederick Ware

Publication number: US20220013161A1

Abstract:
A dynamic random access memory (DRAM) component (e.g., module or integrated circuit) can be configured to have multiple rows in the same bank open concurrently. The controller of the component divides the address space of the banks into segments based on row address ranges. These row address ranges do not necessarily correspond to row address ranges of the bank's subarrays (a.k.a. memory array tiles—MATs). When a command is sent to open a row, the controller marks a plurality of the segments as blocked. The controller thereby tracks address ranges in a bank where it will not open a second row unless and until the first row is closed. The memory component may store information about which, and how many, segments should be blocked in response to opening a row. This information may be read by the controller during initialization.

Publication date: 2022-01-13
Applicant: Rambus Inc
Inventors: Eric John Linstadt

Publication number: –

Abstract:
None

Publication date: –
Applicant: Rambus Inc
Inventors: Dongyun Lee

How are Rambus Inc’s applications performing in USPTO?

Application Number	Title	Status	Art Unit	Examiner
17428105	Memory With Variable Access Granularity	Docketed New Case – Ready for Examination	OPAP	Central, Docket
17390370	Memory System With Multiple Open Rows Per Bank	–	OPAP	Central, Docket
17424254	Memory-Integrated Neural Network	Sent to Classification contractor	OPAP	Central, Docket
17376032	Memory Component With Efficient Write Operations	Docketed New Case – Ready for Examination	OPAP	Central, Docket
17372100	System And Method For Providing A Configurable Timing Control For A Memory System	Docketed New Case – Ready for Examination	OPAP	Central, Docket