Xilinx, Inc Patent Portfolio Statistics

Xilinx, Inc.

Profile Summary

This article summarizes the perfomance of the assignee in the recent years. The overall statistics for this portfolio help to analyze the areas where the assignee is performing well. The filing trend, perfomance across the tech centers and the perfomance of the recent applications has been mentioned below. All the stats are calculated based on the perfomance in USPTO.

How does the overall patent portfolio of Xilinx, Inc. look like?

Assignee Art Units
Total Applications: 4,523 1,662,342
Granted Patents: 4,408 1,087,551
Grant Index 98.97% 83.64%
Abandoned/Rejected Applications: 46 (1.03%) 212,717 (16.36%)
In-Process Applications: 64 362,074
Average Grant Time: 2.63 Years 2.59 Years
Average Office Actions: 1.4 1.48

Which Technology Area Xilinx, Inc. is filing most patents in? (Last 10 years)

Art Unit Definition Total Applications
2819 Semiconductors/Memory 581
2825 Semiconductors/Memory 542
2851 Printing/Measuring and Testing 240
2816 Semiconductors/Memory 210
2842 Electrical Circuits and Systems 123

How many patents are Xilinx, Inc. filing every year?

Year Total Applications Predicted
2022 0* 509
2021 15* 542
2020 109 460
2019 202 202
2018 227
2017 187
2016 174
2015 145
2014 177
2013 135

*The drop in the number of applications filed in last two years compared to previous years is because applications can take up to 18 months to get published

Recently filed patent applications of Xilinx, Inc. in USPTO?

Publication number: US20220092010A1
Application number: 17/457,576

A system can include a plurality of processors. Each processor of the plurality of processors can be configured to execute program code. The system can include a direct memory access system configured for multi-processor operation. The direct memory access system can include a plurality of data engines coupled to a plurality of interfaces via a plurality of switches. The plurality of switches can be programmable to couple different ones of the plurality of data engines to different ones of the plurality of processors for performing direct memory access operations based on a plurality of host profiles corresponding to the plurality of processors.

Publication date: 2022-03-24
Applicant: Xilinx, Inc.
Inventors: Chandrasekhar S Thyamagondlu

Publication number: US20220086042A1
Application number: 17/534,413

A network interface device comprises a plurality of components configured to process a flow of data one after another. A control component is configured to provide one or more control messages in said flow, said one or more control message being provided to said plurality of components one after another such that a configuration of one or more of said components is changed.

Publication date: 2022-03-17
Applicant: Xilinx, Inc.
Inventors: David James Riddoch

Publication number: US20220058005A1
Application number: 17/517,471

Examples herein describe techniques for generating dataflow graphs using source code for defining kernels and communication links between those kernels. In one embodiment, the graph is formed using nodes (e.g., kernels) which are communicatively coupled by edges (e.g., the communication links between the kernels). A compiler converts the source code into a bit stream and/or binary code which configure a heterogeneous processing system of a SoC to execute the graph. The compiler uses the graph expressed in source code to determine where to assign the kernels in the heterogeneous processing system. Further, the compiler can select the specific communication techniques to establish the communication links between the kernels and whether synchronization should be used in a communication link. Thus, the programmer can express the dataflow graph at a high-level (using source code) without understanding about how the operator graph is implemented using the heterogeneous hardware in the SoC.

Publication date: 2022-02-24
Applicant: Xilinx, Inc.
Inventors: B James-Roxby Philip

How are Xilinx, Inc.’s applications performing in USPTO?

Application Number Title Status Art Unit Examiner
17/457,576 Multi-Host Direct Memory Access System For Integrated Circuits Docketed New Case – Ready for Examination OPAP Central, Docket
17/534,413 Network Interface Device Docketed New Case – Ready for Examination OPAP Central, Docket
17/517,471 Dataflow Graph Programming Environment For A Heterogenous Processing System OPAP Central, Docket
17/453,310 Programmable Device Having Hardened Circuits For Predetermined Digital Signal Processing Functionality Docketed New Case – Ready for Examination OPAP Central, Docket
17/515,343 Network Interface Device OPAP Central, Docket