Western Digital Technologies, Inc Patent Portfolio Statistics

Western Digital Technologies, Inc.

Profile Summary

This article summarizes the perfomance of the assignee in the recent years. The overall statistics for this portfolio help to analyze the areas where the assignee is performing well. The filing trend, perfomance across the tech centers and the perfomance of the recent applications has been mentioned below. All the stats are calculated based on the perfomance in USPTO.

How does the overall patent portfolio of Western Digital Technologies, Inc. look like?

Total Applications: 10,007
Granted Patents: 9,216
Grant Index 96.66 %
Abandoned/Rejected Applications: 318 (3.34%)
In-Process Applications: 455
Average Grant Time: 2.59 Years
Average Office Actions: 1.4

Which Technology Area Western Digital Technologies, Inc. is filing most patents in? (Last 10 years)

Art Unit Definition Total Applications
2627 Selective Visual Display Systems 1,539
2688 Telemetry & Code Generation 1,223
2686 Telemetry & Code Generation 551
2651 Videophones & Telephonic Communications 353
2652 Videophones & Telephonic Communications 333

How many patents are Western Digital Technologies, Inc. filing every year?

Year Total Applications
2022 0*
2021 223*
2020 499
2019 445
2018 449

*The drop in the number of applications filed in last two years compared to previous years is because applications can take up to 18 months to get published

Recently filed patent applications of Western Digital Technologies, Inc. in USPTO?

Publication number: US20220028475A1
Application number: 17/494,129

Abstract:
A non-volatile memory system comprises an integrated memory assembly in communication with a memory controller. The integrated memory assembly includes a memory die bonded to a control die. The control die includes one or more control circuits for controlling the operation of the memory die. The control circuits are configured to receive a request to copy data on the memory die, read codewords on the memory die in response to the request, decode the codewords to identify errors in the codewords, correcting the errors in the codewords, and program the codewords back into the memory die. In one embodiment, the codewords read are stored in the memory die as single bit per memory cell data and the codewords programmed back into the memory die after correcting errors are programmed as multiple bit per memory cell data.

Publication date: 2022-01-27
Applicant: Western Digital Technologies, Inc.
Inventors: Eran Sharon


Publication number: US20220027063A1
Application number: 17/493,722

Abstract:
A memory system may include a volatile memory that is configured to store an address data structure that includes a plurality of logical-to-physical address entries. The address data structure may be stored across a plurality of bank groups of the volatile memory. A controller may be configured to store consecutive logical-to-physical address entries across different bank groups. In turn, during read and write operations for data sets associated with consecutive logical addresses, read requests for physical addresses where the data sets are stored may be sent to multiple bank groups and processed by the multiple banks in parallel.

Publication date: 2022-01-27
Applicant: Western Digital Technologies, Inc.
Inventors: Kapil Sundrani


Publication number: US20220019382A1
Application number: 17/490,531

Abstract:
Aspects of a storage device including a memory and a controller are provided which allow for detection of dropped commands based on a die status (ready/busy status) of a command received from a host device. The memory may include dies controlled by chip-enables (CE). After selecting a die using CE, the controller waits between a minimum and maximum time after receiving the command to query the die status, where the minimum time is the time by which the command is expected to begin execution and the maximum time is the shortest time by which the command is expected to complete execution. The controller queries the die status after waiting the time period. If the die status is ready when it should have read busy, the controller detects that the command associated with the data is dropped and requests the host device to reissue the command.

Publication date: 2022-01-20
Applicant: Western Digital Technologies, Inc.
Inventors: Kevin Otoole


How are Western Digital Technologies, Inc.’s applications performing in USPTO?

Application Number Title Status Art Unit Examiner
17/494,129 On-Chip-Copy For Integrated Memory Assembly OPAP Central, Docket
17/493,722 Distribution Of Logical-To-Physical Address Entries Across Multiple Memory Areas OPAP Central, Docket
17/490,531 Nand Dropped Command Detection And Recovery OPAP Central, Docket
17/486,528 Fabric Interconnection For Memory Banks Based On Network-On-Chip Methodology OPAP Central, Docket
17/448,167 Read Head Sensor With Balanced Shield Design OPAP Central, Docket