United Microelectronics Corp Patent Portfolio Statistics

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United Microelectronics Corp.

Profile Summary

This article summarizes the perfomance of the assignee in the recent years. The overall statistics for this portfolio help to analyze the areas where the assignee is performing well. The filing trend, perfomance across the tech centers and the perfomance of the recent applications has been mentioned below. All the stats are calculated based on the perfomance in USPTO.

How does the overall patent portfolio of United Microelectronics Corp. look like?

Assignee Art Units
Total Applications: 6,323 2,331,226
Granted Patents: 4,981 1,565,791
Grant Index 81.07% ↑ 80.35%
Abandoned/Rejected Applications: 1,163 (18.93%) 382,993 (19.65%)
In-Process Applications: 173 382,442
Average Grant Time: 2.02 Years ↓ 2.47 Years
Average Office Actions: 1.33 ↓ 1.4

Which Technology Area United Microelectronics Corp. is filing most patents in? (Last 10 years)

Art Unit Definition Total Applications
2812 Semiconductors/Memory 510
2813 Semiconductors/Memory 451
2818 Semiconductors/Memory 442
2823 Semiconductors/Memory 365
2822 Semiconductors/Memory 345

How many patents are United Microelectronics Corp. filing every year?

Year Total Applications Predicted
2022 0* 614
2021 22* 682
2020 162 579
2019 178 178
2018 302 –
2017 358 –
2016 327 –
2015 348 –
2014 234 –
2013 262 –

*The drop in the number of applications filed in last two years compared to previous years is because applications can take up to 18 months to get published

Recently filed patent applications of United Microelectronics Corp. in USPTO?

Publication number: US20220109104A1
Application number: 17/551,214

Abstract:
A method for fabricating memory device includes: providing a substrate having a bottom electrode layer therein, forming a buffer layer and a mask layer on the buffer layer over the substrate, in contact with the bottom electrode layer, performing an advanced oxidation process on a sidewall of the buffer layer to form a resistive layer, which surrounds the whole sidewall of the buffer layer and extends upward vertically from the substrate, and forming, over the substrate, a noble metal layer and a top electrode layer on the noble metal layer, fully covering the resistive layer and the mask layer.

Publication date: 2022-04-07
Applicant: United Microelectronics Corp.
Inventors: Huakai Li

Publication number: US20220093782A1
Application number: 17/544,846

Abstract:
A high electron mobility transistor includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer and the second III-V compound layer are different from each other. A shallow recess, a first deep recess and a second deep recess are disposed in the second III-V compound layer. The first deep recess and the second deep recess are respectively disposed at two sides of the shallow recess. The source electrode fills in the first deep recess and contacts the top surface of the first III-V compound layer. A drain electrode fills in the second deep recess and contacts the top surface of the first III-V compound layer. The shape of the source electrode and the shape of the drain electrode are different from each other. A gate electrode is disposed directly on the shallow recess.

Publication date: 2022-03-24
Applicant: United Microelectronics Corp.
Inventors: Hsieh Po-Kuang

Publication number: US20220093783A1
Application number: 17/544,867

Abstract:
A high electron mobility transistor includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer and the second III-V compound layer are different from each other. A shallow recess, a first deep recess and a second deep recess are disposed in the second III-V compound layer. The first deep recess and the second deep recess are respectively disposed at two sides of the shallow recess. The source electrode fills in the first deep recess and contacts the top surface of the first III-V compound layer. A drain electrode fills in the second deep recess and contacts the top surface of the first III-V compound layer. The shape of the source electrode and the shape of the drain electrode are different from each other. A gate electrode is disposed directly on the shallow recess.

Publication date: 2022-03-24
Applicant: United Microelectronics Corp.
Inventors: Hsieh Po-Kuang

How are United Microelectronics Corp.’s applications performing in USPTO?

Application Number Title Status Art Unit Examiner
17/551,214 Fabrication Method Of Memory Device Docketed New Case – Ready for Examination OPAP Central, Docket
17/544,846 Hemt And Method Of Fabricating The Same Docketed New Case – Ready for Examination OPAP Central, Docket
17/544,867 Hemt And Method Of Fabricating The Same Docketed New Case – Ready for Examination OPAP Central, Docket
17/533,003 Semiconductor Device And Method For Fabricating The Same Docketed New Case – Ready for Examination OPAP Central, Docket