Tokyo Electron Limited Patent Portfolio Statistics

Publication number: US20220028659A1
Application number: 17/498,063

Abstract:
An exemplary plasma processing system includes a plasma processing chamber, an electrode for powering plasma in the plasma processing chamber, a tunable radio frequency (RF) signal generator configured to output a first signal at a first frequency and a second signal at a second frequency. The second frequency is at least 1.1 times the first frequency. The system includes a broadband power amplifier coupled to the tunable RF signal generator, the first frequency and the second frequency being within an operating frequency range of the broadband power amplifier. The output of the broadband power amplifier is coupled to the electrode. The broadband power amplifier is configured to supply, at the output, first power at the first frequency and second power at the second frequency.

Publication date: 2022-01-27
Applicant: Tokyo Electron Limited
Inventors: Peter Ventzek

---

Publication number: US20220028665A1
Application number: 17/495,908

Abstract:
A decrease of an etching rate of a substrate can be suppressed, and energy of ions irradiated to an inner wall of a chamber main body can be reduced. A plasma processing apparatus includes a DC power supply configured to generate a negative DC voltage to be applied to a lower electrode of a stage. In a plasma processing performed by using the plasma processing apparatus, a radio frequency power is supplied to generate plasma by exciting a gas within a chamber. Further, the negative DC voltage from the DC power supply is periodically applied to the lower electrode to attract ions in the plasma onto the substrate placed on the stage. A ratio occupied, within each of cycles, by a period during which the DC voltage is applied to the lower electrode is set to be equal to or less than 40%.

Publication date: 2022-01-27
Applicant: Tokyo Electron Limited
Inventors: Himori Shinji

---

Publication number: US20220020642A1
Application number: 17/487,987

Abstract:
Methods are disclosed that provide improved via profile control by forming atomic layer deposition (ALD) liners to protect side walls of vias during subsequent etch processes. ALD liners can be used for BEOL etch processes as well as for full self-aligned via (FSAV) processes and/or other processes. For one embodiment, ALD liners are used as protection or sacrificial layers for vias to reduce damage during multilayer via or trench etch processes. The ALD liners can also be deposited at different points within process flows, for example, before or after removal of organic planarization layers. The use of ALD liners facilitates shrinking of via critical dimensions (CDs) while still controlling via profiles for various process applications including dual Damascene processes and FSAV processes. In addition, the use of ALD liners improves overall CD control for via or hole formation as well as device yield and reliability.

Publication date: 2022-01-20
Applicant: Tokyo Electron Limited
Inventors: Sun Xinghua

---