Taiwan Semiconductor Manufacturing Company, Ltd Patent Portfolio Statistics

Publication number: US20220026812A1
Application number: 17/498,948

Abstract:
A mask layout containing a non-Manhattan pattern is received. The received mask layout is processed. An edge of the non-Manhattan pattern is identified. A plurality of two-dimensional kernels is generated based on processed pre-selected mask layout samples. The two-dimensional kernels each have a respective rotational symmetry. The two-dimensional kernels are applied to the edge of the non-Manhattan pattern to obtain a correction field for the non-Manhattan pattern. A thin mask model is applied to the non-Manhattan pattern. The thin mask model contains a binary modeling of the non-Manhattan pattern. A near field of the non-Manhattan pattern is determined by applying the correction field to the non-Manhattan pattern having the thin mask model applied thereon. An optical model is applied to the near field to obtain an aerial image on a wafer. A resist model is applied to the aerial image to obtain a final resist image on the wafer.

Publication date: 2022-01-27
Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
Inventors: Xin Zhou

---

Publication number: US20220028985A1
Application number: 17/499,364

Abstract:
Various embodiments provide a flash memory with an improved gate structure and a method of creating the same. The flash memory includes a plurality of memory cells that include a memory gate, a selection gate, a gate dielectric layer, and a protective cap formed on an upper surface of the gate dielectric layer. The protective cap protects the gate dielectric layer, and prevents the memory and selection gates from being unintentionally electrically connected to each other by conductive material.

Publication date: 2022-01-27
Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
Inventors: Chen Sheng-Chieh

---

Publication number: US20220028974A1
Application number: 17/498,593

Abstract:
A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.

Publication date: 2022-01-27
Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
Inventors: Chiang Hung-Li

---