Taiwan Semiconductor Manufacturing Co., Ltd Patent Portfolio Statistics

Taiwan Semiconductor Manufacturing Co., Ltd.

Profile Summary

This article summarizes the perfomance of the assignee in the recent years. The overall statistics for this portfolio help to analyze the areas where the assignee is performing well. The filing trend, perfomance across the tech centers and the perfomance of the recent applications has been mentioned below. All the stats are calculated based on the perfomance in USPTO.

How does the overall patent portfolio of Taiwan Semiconductor Manufacturing Co., Ltd. look like?

Total Applications: 12,570
Granted Patents: 10,034
Grant Index 95.05 %
Abandoned/Rejected Applications: 522 (4.95%)
In-Process Applications: 1,961
Average Grant Time: 2.23 Years
Average Office Actions: 1.48

Which Technology Area Taiwan Semiconductor Manufacturing Co., Ltd. is filing most patents in? (Last 10 years)

Art Unit Definition Total Applications
2818 Semiconductors/Memory 680
2814 Semiconductors/Memory 572
2813 Semiconductors/Memory 529
2812 Semiconductors/Memory 508
Opap Parked GAU 486

How many patents are Taiwan Semiconductor Manufacturing Co., Ltd. filing every year?

Year Total Applications
2022 0*
2021 532*
2020 1,728
2019 1,730
2018 1,379

*The drop in the number of applications filed in last two years compared to previous years is because applications can take up to 18 months to get published

Recently filed patent applications of Taiwan Semiconductor Manufacturing Co., Ltd. in USPTO?

Publication number: US20220026812A1
Application number: 17/498,948

Abstract:
A mask layout containing a non-Manhattan pattern is received. The received mask layout is processed. An edge of the non-Manhattan pattern is identified. A plurality of two-dimensional kernels is generated based on processed pre-selected mask layout samples. The two-dimensional kernels each have a respective rotational symmetry. The two-dimensional kernels are applied to the edge of the non-Manhattan pattern to obtain a correction field for the non-Manhattan pattern. A thin mask model is applied to the non-Manhattan pattern. The thin mask model contains a binary modeling of the non-Manhattan pattern. A near field of the non-Manhattan pattern is determined by applying the correction field to the non-Manhattan pattern having the thin mask model applied thereon. An optical model is applied to the near field to obtain an aerial image on a wafer. A resist model is applied to the aerial image to obtain a final resist image on the wafer.

Publication date: 2022-01-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventors: Xin Zhou


Publication number: US20220028985A1
Application number: 17/499,364

Abstract:
Various embodiments provide a flash memory with an improved gate structure and a method of creating the same. The flash memory includes a plurality of memory cells that include a memory gate, a selection gate, a gate dielectric layer, and a protective cap formed on an upper surface of the gate dielectric layer. The protective cap protects the gate dielectric layer, and prevents the memory and selection gates from being unintentionally electrically connected to each other by conductive material.

Publication date: 2022-01-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventors: Chen Sheng-Chieh


Publication number: US20220028974A1
Application number: 17/498,593

Abstract:
A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.

Publication date: 2022-01-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventors: Chiang Hung-Li


How are Taiwan Semiconductor Manufacturing Co., Ltd.’s applications performing in USPTO?

Application Number Title Status Art Unit Examiner
17/498,948 Method Of Modeling A Mask Having Patterns With Arbitrary Angles OPAP Central, Docket
17/499,364 Flash Memory With Improved Gate Structure And A Method Of Creating The Same OPAP Central, Docket
17/498,593 Semiconductor Device And Manufacturing Method Thereof OPAP Central, Docket
17/498,543 Pellicle For An Euv Lithography Mask And A Method Of Manufacturing Thereof OPAP Central, Docket
17/498,645 Method Of Fabricating A Semiconductor Device OPAP Central, Docket