Taiwan Semiconductor Manufacturing Co., Ltd Patent Portfolio Statistics

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Taiwan Semiconductor Manufacturing Co., Ltd.

Profile Summary

This article summarizes the perfomance of the assignee in the recent years. The overall statistics for this portfolio help to analyze the areas where the assignee is performing well. The filing trend, perfomance across the tech centers and the perfomance of the recent applications has been mentioned below. All the stats are calculated based on the perfomance in USPTO.

How does the overall patent portfolio of Taiwan Semiconductor Manufacturing Co., Ltd. look like?

Assignee Art Units
Total Applications: 12,570 2,238,189
Granted Patents: 10,034 1,503,584
Grant Index 95.05% ↑ 81.03%
Abandoned/Rejected Applications: 522 (4.95%) 352,066 (18.97%)
In-Process Applications: 1,961 382,539
Average Grant Time: 2.23 Years ↓ 2.45 Years
Average Office Actions: 1.48 ↑ 1.39

Which Technology Area Taiwan Semiconductor Manufacturing Co., Ltd. is filing most patents in? (Last 10 years)

Art Unit Definition Total Applications
2818 Semiconductors/Memory 680
2814 Semiconductors/Memory 572
2813 Semiconductors/Memory 529
2812 Semiconductors/Memory 508
Opap Parked GAU 486

How many patents are Taiwan Semiconductor Manufacturing Co., Ltd. filing every year?

Year Total Applications Predicted
2022 0* 2466
2021 532* 2327
2020 1,728 2110
2019 1,730 1730
2018 1,379 –
2017 1,040 –
2016 824 –
2015 533 –
2014 424 –
2013 510 –

*The drop in the number of applications filed in last two years compared to previous years is because applications can take up to 18 months to get published

Recently filed patent applications of Taiwan Semiconductor Manufacturing Co., Ltd. in USPTO?

Publication number: None
Application number: 63/310,478

Abstract:
–

Publication date: –
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventors: I-Wen Wang

Publication number: US20220108956A1
Application number: 17/554,552

Abstract:
A method for forming a package structure is provided. The method includes forming first conductive structures and a first semiconductor die on a same side of a redistribution structure. The method includes forming an interposer substrate over the redistribution structure, wherein the first semiconductor die is between the interposer substrate and the redistribution structure, and edges of the interposer substrate extend beyond edges of the first semiconductor die. The method includes forming a second semiconductor die on the redistribution structure, wherein the first semiconductor die and the second semiconductor die are disposed on opposite sides of the redistribution structure.

Publication date: 2022-04-07
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventors: Jeng Shin-Puu

Publication number: US20220108967A1
Application number: 17/554,475

Abstract:
A chip package structure is provided. The chip package structure includes a first redistribution structure having a first surface and a second surface opposite to the first surface. The chip package structure includes a first chip over the first surface. The chip package structure includes a first conductive bump connected between the first chip and the first redistribution structure. The chip package structure includes a first conductive pillar over the first surface and electrically connected to the first redistribution structure. The chip package structure includes a second chip over the second surface. The chip package structure includes a second conductive bump connected between the second chip and the first redistribution structure. The chip package structure includes a second conductive pillar over the second surface and electrically connected to the first redistribution structure.

Publication date: 2022-04-07
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventors: Chen Shuo-Mao

How are Taiwan Semiconductor Manufacturing Co., Ltd.’s applications performing in USPTO?

Application Number Title Status Art Unit Examiner
63/310,478 Layout And Structure Floorplan Technique For Aoi/Oai Application Dispatched from Preexam, Not Yet Docketed – –
17/554,552 Formation Method Of Chip Package With Fan-Out Feature Docketed New Case – Ready for Examination OPAP Central, Docket
17/554,475 Chip Package Structure Docketed New Case – Ready for Examination OPAP Central, Docket
17/554,811 Input/Output Semiconductor Devices Docketed New Case – Ready for Examination OPAP Central, Docket
17/554,503 Converter And Conversion Method For Converting Click Position Of Display Into Light Pen Simulated Signal For Semiconductor Manufacturing Machine Docketed New Case – Ready for Examination OPAP Central, Docket