Synopsys, Inc Patent Portfolio Statistics
Profile Summary
This article summarizes the perfomance of the assignee in the recent years. The overall statistics for this portfolio help to analyze the areas where the assignee is performing well. The filing trend, perfomance across the tech centers and the perfomance of the recent applications has been mentioned below. All the stats are calculated based on the perfomance in USPTO.
How does the overall patent portfolio of Synopsys, Inc. look like?
Total Applications: | 2,671 |
Granted Patents: | 2,447 |
Grant Index | 95.85 % |
Abandoned/Rejected Applications: | 106 (4.15%) |
In-Process Applications: | 111 |
Average Grant Time: | 2.86 Years |
Average Office Actions: | 1.52 |
Which Technology Area Synopsys, Inc. is filing most patents in? (Last 10 years)
Art Unit | Definition | Total Applications |
2825 | Semiconductors/Memory | 589 |
2851 | Printing/Measuring and Testing | 559 |
2824 | Semiconductors/Memory | 111 |
2827 | Semiconductors/Memory | 87 |
2123 | AI & Simulation/Modeling | 72 |
How many patents are Synopsys, Inc. filing every year?
Year | Total Applications |
2022 | 0* |
2021 | 41* |
2020 | 63 |
2019 | 91 |
2018 | 89 |
*The drop in the number of applications filed in last two years compared to previous years is because applications can take up to 18 months to get published
Recently filed patent applications of Synopsys, Inc. in USPTO?
Application number: 17/438,521
Abstract:
None
Publication date: –
Applicant: Synopsys, Inc.
Inventors: Emil Gizdarski
Publication number: –
Application number: 17/433,595
Abstract:
None
Publication date: –
Applicant: Synopsys, Inc.
Inventors: Chai Wenwen
Publication number: US20210374313A1
Application number: 17/400,360
Abstract:
Publication date: 2021-12-02
Applicant: Synopsys, Inc.
Inventors: Jerzy Michal Rewienski
How are Synopsys, Inc.’s applications performing in USPTO?
Application Number | Title | Status | Art Unit | Examiner |
17/438,521 | Single-Pass Diagnosis For Multiple Chain Defects | – | – | – |
17/433,595 | Method To Compute Timing Yield And Yield Bottleneck Using Correlated Sample Generation And Efficient Statistical Simulation | – | – | – |
17/400,360 | Finding Equivalent Classes Of Hard Defects In Stacked Mosfet Arrays | Docketed New Case – Ready for Examination | OPAP | Central, Docket |
17/383,869 | Memory Efficient Scalable Distributed Static Timing Analysis Using Structure Based Self-Aligned Parallel Partitioning | – | OPAP | Central, Docket |
17/377,080 | Sequential Delay Enabler Timer Circuit For Low Voltage Operation For Srams | – | OPAP | Central, Docket |