Synopsys, Inc Patent Portfolio Statistics

Synopsys, Inc.

Profile Summary

This article summarizes the perfomance of the assignee in the recent years. The overall statistics for this portfolio help to analyze the areas where the assignee is performing well. The filing trend, perfomance across the tech centers and the perfomance of the recent applications has been mentioned below. All the stats are calculated based on the perfomance in USPTO.

How does the overall patent portfolio of Synopsys, Inc. look like?

Assignee Art Units
Total Applications: 2,671 1,768,135
Granted Patents: 2,447 1,158,722
Grant Index 95.85% 82.42%
Abandoned/Rejected Applications: 106 (4.15%) 247,201 (17.58%)
In-Process Applications: 111 362,212
Average Grant Time: 2.86 Years 2.65 Years
Average Office Actions: 1.52 1.49

Which Technology Area Synopsys, Inc. is filing most patents in? (Last 10 years)

Art Unit Definition Total Applications
2825 Semiconductors/Memory 589
2851 Printing/Measuring and Testing 559
2824 Semiconductors/Memory 111
2827 Semiconductors/Memory 87
2123 AI & Simulation/Modeling 72

How many patents are Synopsys, Inc. filing every year?

Year Total Applications Predicted
2022 0* 587
2021 41* 499
2020 63 437
2019 91 91
2018 89
2017 115
2016 111
2015 116
2014 134
2013 140

*The drop in the number of applications filed in last two years compared to previous years is because applications can take up to 18 months to get published

Recently filed patent applications of Synopsys, Inc. in USPTO?

Publication number: US20220189973A1
Application number: 17/544,583

A one-transistor (1T) one-time programmable (OTP) anti-fuse bitcell is provided. The 1T OTP anti-fuse bitcell includes a gate, a diffusion region including at least two sub-regions, and a gate oxide region located between the gate and the diffusion region, the gate oxide region including a thin gate oxide region and a thick gate oxide region.

Publication date: 2022-06-16
Applicant: Synopsys, Inc.
Inventors: Andrew Edward Horch

Publication number: US20220066909A1
Application number: 17/454,589

A process is disclosed to identify the minimal set of sequential and combinational signals needed to fully reconstruct the combinational layout after emulation is complete. A minimal subset of sequential and combinational elements is output from the emulator to maximize the emulator speed and limit the utilization of emulator resources, e.g., FPGA resources. An efficient reconstruction of combinational waveforms or SAIF data is performed using a parallel computing grid.

Publication date: 2022-03-03
Applicant: Synopsys, Inc.
Inventors: Rahim Solaiman

Publication number: US20220146945A1
Application number: 17/522,574

In some aspects, a mask pattern is accessed. The mask pattern is for use in a lithography process that prints a pattern on a wafer. The mask pattern is applied as input to a deterministic model of the lithography process to predict a characteristic of the printed pattern. The deterministic model is deterministic, but it accounts for local stochastic variations of the characteristic in the printed pattern.

Publication date: 2022-05-12
Applicant: Synopsys, Inc.
Inventors: Kandel Prasad Yudhishthir

How are Synopsys, Inc.’s applications performing in USPTO?

Application Number Title Status Art Unit Examiner
17/544,583 One-Transistor (1T) One-Time Programmable (Otp) Anti-Fuse Bitcell With Reduced Threshold Voltage OPAP Central, Docket
17/454,589 Waveform Based Reconstruction For Emulation Docketed New Case – Ready for Examination OPAP Central, Docket
17/522,574 Stochastic-Aware Lithographic Models For Mask Synthesis Docketed New Case – Ready for Examination OPAP Central, Docket
17/520,050 Common Mode Logic Based Quadrature Coupled Injection Locked Frequency Divider With Internal Power-Supply Jitter Compensation Docketed New Case – Ready for Examination 2849 Cheng, Diana
17/518,024 Reformatting Scan Patterns In Presence Of Hold Type Pipelines Docketed New Case – Ready for Examination OPAP Central, Docket