Sk Hynix Inc Patent Portfolio Statistics

Sk Hynix Inc.

Profile Summary

This article summarizes the perfomance of the assignee in the recent years. The overall statistics for this portfolio help to analyze the areas where the assignee is performing well. The filing trend, perfomance across the tech centers and the perfomance of the recent applications has been mentioned below. All the stats are calculated based on the perfomance in USPTO.

How does the overall patent portfolio of Sk Hynix Inc. look like?

Total Applications: 9,364
Granted Patents: 7,211
Grant Index 88.57 %
Abandoned/Rejected Applications: 931 (11.43%)
In-Process Applications: 1,172
Average Grant Time: 1.88 Years
Average Office Actions: 1.13

Which Technology Area Sk Hynix Inc. is filing most patents in? (Last 10 years)

Art Unit Definition Total Applications
2827 Semiconductors/Memory 1,191
2824 Semiconductors/Memory 1,082
2825 Semiconductors/Memory 625
2842 Electrical Circuits and Systems 547
2112 Computer Error Control, Reliability, & Control Systems 324

How many patents are Sk Hynix Inc. filing every year?

Year Total Applications
2022 0*
2021 495*
2020 1,028
2019 1,024
2018 1,028

*The drop in the number of applications filed in last two years compared to previous years is because applications can take up to 18 months to get published

Recently filed patent applications of Sk Hynix Inc. in USPTO?

Publication number: US20220027131A1
Application number: 17/499,331

Abstract:
A processing-in-memory (PIM) device includes first to Lth multiplication/accumulation (MAC) operators, first to Lth memory banks, first to Lth additional adders, and a plurality of data input/output (I/O) circuits. The first to Lth MAC operators include first to Lth left MAC operators and first to Lth right MAC operators. The first to Lth additional adders are configured to generate and output first to Mth MAC result data. The plurality of data I/O circuits include left data I/O circuits and right data I/O circuits. Each of the first to Lth additional adders is classified as either a left additional adder or a right additional adder. The left additional adders are configured to transmit a first portion of the first to Mth MAC result data to the left data I/O circuits, and the right additional adders are configured to transmit a second portion of the first to Mth MAC result data to the right data I/O circuits.

Publication date: 2022-01-27
Applicant: Sk Hynix Inc.
Inventors: Choung Ki Song


Publication number: US20220028931A1
Application number: 17/498,849

Abstract:
An electronic device including a semiconductor memory is provided. The semiconductor memory includes: a substrate having a substantially horizontal upper surface; first to Nth layers (where N is a natural number of two or more) disposed in horizontal layers on the substrate and spaced apart from each other above the substrate in a vertical direction, wherein each of the first to Nth layers includes a plurality of conductive lines; an insulating layer disposed to fill spaces between the conductive lines; a hole having sidewalls that extends in the vertical direction through the conductive lines of the first to Nth layers and the insulating layer therebetween; a variable resistance layer disposed on the sidewalls of the hole; and a conductive pillar disposed to fill the hole in which the variable resistance layer is formed.

Publication date: 2022-01-27
Applicant: Sk Hynix Inc.
Inventors: Lee Se-Ho


Publication number: US20220028806A1
Application number: 17/498,177

Abstract:
A semiconductor package includes a substrate and a semiconductor chip disposed over the substrate. The substrate includes: a base layer including an upper surface facing the semiconductor chip; an upper ground electrode plate disposed over the upper surface of the base layer and configured to transmit a ground voltage to the semiconductor chip; and a dummy power pattern disposed in the upper ground electrode plate and having a side surface which is surrounded by the upper ground electrode plate and is spaced apart from the upper ground electrode plate with an insulating material between the dummy power pattern and the upper ground electrode plate. A ground voltage transmission path from the upper ground electrode plate to the semiconductor chip is spaced apart from the dummy power pattern.

Publication date: 2022-01-27
Applicant: Sk Hynix Inc.
Inventors: Cho Ho Hyung


How are Sk Hynix Inc.’s applications performing in USPTO?

Application Number Title Status Art Unit Examiner
17/499,331 Processing-In-Memory (Pim) Devices OPAP Central, Docket
17/498,849 Semiconductor Memory Device Having A Variable Resistence Layer OPAP Central, Docket
17/498,177 Semiconductor Package Including Decoupling Capacitor OPAP Central, Docket
17/496,561 Repair Analysis Circuit And Memory Including The Same OPAP Central, Docket
17/496,537 Repair Analysis Circuit And Memory Including The Same OPAP Central, Docket