Sk Hynix Inc Patent Portfolio Statistics

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Sk Hynix Inc.

Profile Summary

This article summarizes the perfomance of the assignee in the recent years. The overall statistics for this portfolio help to analyze the areas where the assignee is performing well. The filing trend, perfomance across the tech centers and the perfomance of the recent applications has been mentioned below. All the stats are calculated based on the perfomance in USPTO.

How does the overall patent portfolio of Sk Hynix Inc. look like?

Assignee Art Units
Total Applications: 9,364 1,806,821
Granted Patents: 7,211 1,214,191
Grant Index 88.57% ↑ 84.5%
Abandoned/Rejected Applications: 931 (11.43%) 222,743 (15.5%)
In-Process Applications: 1,172 369,887
Average Grant Time: 1.88 Years ↓ 2.45 Years
Average Office Actions: 1.13 ↓ 1.39

Which Technology Area Sk Hynix Inc. is filing most patents in? (Last 10 years)

Art Unit Definition Total Applications
2827 Semiconductors/Memory 1,191
2824 Semiconductors/Memory 1,082
2825 Semiconductors/Memory 625
2842 Electrical Circuits and Systems 547
2112 Computer Error Control, Reliability, & Control Systems 324

How many patents are Sk Hynix Inc. filing every year?

Year Total Applications Predicted
2022 0* 1404
2021 495* 1314
2020 1,028 1276
2019 1,024 1024
2018 1,028 –
2017 955 –
2016 985 –
2015 910 –
2014 1,002 –
2013 747 –

*The drop in the number of applications filed in last two years compared to previous years is because applications can take up to 18 months to get published

Recently filed patent applications of Sk Hynix Inc. in USPTO?

Publication number: US20220102376A1
Application number: 17/549,456

Abstract:
A semiconductor device, and method of manufacturing a semiconductor device, includes second conductive patterns separated from each other above a first stack structure which is penetrated by first channel structures and enclosing second channel structures coupled to the first channel structures, respectively. Each of the second conductive patterns includes electrode portions stacked in a first direction and at least one connecting portion extending in the first direction to be coupled to the electrode portions.

Publication date: 2022-03-31
Applicant: Sk Hynix Inc.
Inventors: Shin Sup Wan

Publication number: US20220188015A1
Application number: 17/549,671

Abstract:
A semiconductor memory device comprises: first storage logic configured to store, as first addresses, ‘K’ addresses having different values among input addresses applied during the enable period of a reference signal, second storage logic configured to store, as second addresses, ‘L’ addresses corresponding to a time point at which the enable period of the reference signal is ended among the input addresses, an order controller configured to determine a first output order of each of the first addresses based on a number of times each of the first addresses is repeatedly input, and to determine a second output order for outputting mixed addresses obtained by mixing the first addresses based on the first output order and the second addresses together, and refresh operation logic configured to apply the mixed addresses according to the second output order, to a target refresh operation.

Publication date: 2022-06-16
Applicant: Sk Hynix Inc.
Inventors: Hwang Jeong Tae

Publication number: US20220103176A1
Application number: 17/549,316

Abstract:
The present technology may include: a first logic gate coupled to an internal voltage terminal and configured to receive data and invert and output the data according to a first enable signal; and a second logic gate coupled to the internal voltage terminal and configured to invert an output of the first logic gate and to output an inverted output as a first buffer signal according to the first enable signal, and configured to compensate for a duty skew of the first buffer signal according to a level of an external voltage.

Publication date: 2022-03-31
Applicant: Sk Hynix Inc.
Inventors: Han Jeong Yo

How are Sk Hynix Inc.’s applications performing in USPTO?

Application Number Title Status Art Unit Examiner
17/549,456 Semiconductor Device And Manufacturing Method Of The Semiconductor Device Docketed New Case – Ready for Examination OPAP Central, Docket
17/549,671 Apparatus And Method For Performing Target Refresh Operation – OPAP Central, Docket
17/549,316 Buffer Circuit, Receiver Circuit Including The Buffer Circuit, And Semiconductor Apparatus Including The Receiver Circuit Docketed New Case – Ready for Examination OPAP Central, Docket
17/549,633 Apparatus And Method For Performing Target Refresh Operation – OPAP Central, Docket
17/544,478 Amplifier And Receiving Circuit, Semiconductor Apparatus, And Semiconductor System Using The Same Docketed New Case – Ready for Examination OPAP Central, Docket