Sandisk Technologies Llc Patent Portfolio Statistics

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Sandisk Technologies Llc

Profile Summary

This article summarizes the perfomance of the assignee in the recent years. The overall statistics for this portfolio help to analyze the areas where the assignee is performing well. The filing trend, perfomance across the tech centers and the perfomance of the recent applications has been mentioned below. All the stats are calculated based on the perfomance in USPTO.

How does the overall patent portfolio of Sandisk Technologies Llc look like?

Assignee Art Units
Total Applications: 6,572 1,739,558
Granted Patents: 5,637 1,121,149
Grant Index 89.24% ↑ 81.87%
Abandoned/Rejected Applications: 680 (10.76%) 248,250 (18.13%)
In-Process Applications: 250 370,159
Average Grant Time: 2.37 Years ↓ 2.53 Years
Average Office Actions: 1.32 ↓ 1.48

Which Technology Area Sandisk Technologies Llc is filing most patents in? (Last 10 years)

Art Unit Definition Total Applications
2827 Semiconductors/Memory 1,050
2824 Semiconductors/Memory 842
2818 Semiconductors/Memory 285
2825 Semiconductors/Memory 271
2112 Computer Error Control, Reliability, & Control Systems 209

How many patents are Sandisk Technologies Llc filing every year?

Year Total Applications Predicted
2022 0* 834
2021 26* 828
2020 265 734
2019 298 298
2018 275 –
2017 273 –
2016 330 –
2015 554 –
2014 631 –
2013 528 –

*The drop in the number of applications filed in last two years compared to previous years is because applications can take up to 18 months to get published

Recently filed patent applications of Sandisk Technologies Llc in USPTO?

Publication number: US20220139878A1
Application number: 17/090,045

Abstract:
A semiconductor structure includes a peripheral circuit, a first three-dimensional memory array overlying the peripheral circuit and including a first alternating stack of first insulating layers and first electrically conductive layers containing first word lines and first select lines, and first memory stack structures vertically extending through the first alternating stack, and a second three-dimensional memory array overlying the first three-dimensional memory array and including a second alternating stack of second insulating layers and second electrically conductive layers containing second word lines and second select lines, and second memory stack structures vertically extending through the second alternating stack. The peripheral circuit includes a first word line driver circuit having first word line driver output nodes electrically connected to at least some of the first word lines and at least some of the second word lines, and each first word line is electrically connected to a respective second word line.

Publication date: 2022-05-05
Applicant: Sandisk Technologies Llc
Inventors: Ken Oowada

Publication number: US20220139441A1
Application number: 17/090,080

Abstract:
A semiconductor structure includes a peripheral circuit, a first three-dimensional memory array overlying the peripheral circuit and including a first alternating stack of first insulating layers and first electrically conductive layers containing first word lines and first select lines, and first memory stack structures vertically extending through the first alternating stack, and a second three-dimensional memory array overlying the first three-dimensional memory array and including a second alternating stack of second insulating layers and second electrically conductive layers containing second word lines and second select lines, and second memory stack structures vertically extending through the second alternating stack. The peripheral circuit includes a first word line driver circuit having first word line driver output nodes electrically connected to at least some of the first word lines and at least some of the second word lines, and each first word line is electrically connected to a respective second word line.

Publication date: 2022-05-05
Applicant: Sandisk Technologies Llc
Inventors: Ken Oowada

Publication number: US20220130853A1
Application number: 17/082,629

Abstract:
A memory die includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, a memory opening fill structure located in the memory opening and including a memory film, a vertical semiconductor channel, a source region containing a metal silicide material contacting a first end of the vertical semiconductor channel, and a drain region containing a doped semiconductor material contacting a second end of the vertical semiconductor channel, and a source contact layer contacting the source region.

Publication date: 2022-04-28
Applicant: Sandisk Technologies Llc
Inventors: Rahul Sharangpani

How are Sandisk Technologies Llc’s applications performing in USPTO?

Application Number Title Status Art Unit Examiner
17/090,045 Three-Dimensional Memory Device Containing A Shared Word Line Driver Across Different Tiers And Methods For Making The Same Patented Case 2817 Tran, Thanh Y
17/090,080 Three-Dimensional Memory Device Containing A Shared Word Line Driver Across Different Tiers And Methods For Making The Same Final Rejection Mailed 2827 Hoang, Huan
17/082,629 Three-Dimensional Memory Device Including Metal Silicide Source Regions And Methods For Forming The Same Notice of Allowance Mailed — Application Received in Office of Publications 2817 Goodwin, David J
17/066,663 Wordline Voltage Overdrive Methods And Systems Patented Case 2824 Byrne, Harry W
16/687,086 Core Controller Architecture Abandoned — Failure to Respond to an Office Action 2139 Kortman, Curtis James