Rambus Inc Patent Portfolio Statistics

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Rambus Inc.

Profile Summary

This article summarizes the perfomance of the assignee in the recent years. The overall statistics for this portfolio help to analyze the areas where the assignee is performing well. The filing trend, perfomance across the tech centers and the perfomance of the recent applications has been mentioned below. All the stats are calculated based on the perfomance in USPTO.

How does the overall patent portfolio of Rambus Inc. look like?

Assignee Art Units
Total Applications: 2,129 1,810,408
Granted Patents: 1,822 1,197,889
Grant Index 91.56% ↑ 82.8%
Abandoned/Rejected Applications: 168 (8.44%) 248,801 (17.2%)
In-Process Applications: 135 363,718
Average Grant Time: 2.55 Years ↓ 2.6 Years
Average Office Actions: 1.55 ↑ 1.46

Which Technology Area Rambus Inc. is filing most patents in? (Last 10 years)

Art Unit Definition Total Applications
2827 Semiconductors/Memory 136
2611 Computer Graphic Processing, 3D Animation, Display Color Attribute, Object Processing, Hardware and Memory 111
2824 Semiconductors/Memory 95
2631 Digital and Optical Communications 78
2632 Digital and Optical Communications 67

How many patents are Rambus Inc. filing every year?

Year Total Applications Predicted
2022 0* 213
2021 45* 287
2020 43 262
2019 35 35
2018 21 –
2017 25 –
2016 167 –
2015 188 –
2014 178 –
2013 155 –

*The drop in the number of applications filed in last two years compared to previous years is because applications can take up to 18 months to get published

Recently filed patent applications of Rambus Inc. in USPTO?

Publication number: None
Application number: 17/627,478

Abstract:
–

Publication date: –
Applicant: Rambus Inc.
Inventors: Thomas Vogelsang

Publication number: US20220190846A1
Application number: 17/548,176

Abstract:
An integrated circuit (IC) device is disclosed. The IC device includes an error encoder to receive a word of k bits and to encode the word using a G-matrix to generate an encoded word of n bits. The n bits include the k bits and n-k check bits. The G matrix is based on a parity check matrix defining a single error correct, double error detect, and burst error detect (SECDEDBED) code. An error decoder receives the encoded word and applies the parity check matrix to the encoded word. The parity check matrix is configured to generate a syndrome from the encoded word. The syndrome being used to detect a random double bit error, a random single bit error, and a burst error of between two and m bits within m adjacent bits of an m-bit subset of the data word starting from an m-bit boundary of the word of k bits, and where m <n-k.

Publication date: 2022-06-16
Applicant: Rambus Inc.
Inventors: Imel Michael Thomas

Publication number: US20220179556A1
Application number: 17/544,584

Abstract:
An integrated circuit (IC) memory device includes an array of storage cells configured into multiple banks. Interface circuitry receives refresh commands from a host memory controller to refresh the multiple banks for a first refresh mode. On-die refresh control circuitry selectively generates local refresh commands to refresh the multiple banks in cooperation with the host memory controller during a designated hidden refresh interval in a second refresh mode. Mode register circuitry stores a value indicating whether the on-die refresh control circuitry is enabled for use during the second refresh mode. The interface circuitry includes backchannel control circuitry to transmit a corrective action control signal during operation in the second refresh mode.

Publication date: 2022-06-09
Applicant: Rambus Inc.
Inventors: Thomas Vogelsang

How are Rambus Inc.’s applications performing in USPTO?

Application Number Title Status Art Unit Examiner
17/627,478 Compute Accelerated Stacked Memory Docketed New Case – Ready for Examination OPAP Central, Docket
17/548,176 Single Error Correct Double Error Detect (Secded) Error Coding With Burst Error Detection Capability – OPAP Central, Docket
17/544,584 Memory Device Having Hidden Refresh – OPAP Central, Docket
17/543,449 Heterogenous-Latency Memory Optimization – OPAP Central, Docket
17/532,865 Circuits And Methods For Detecting And Unlocking Edge-Phase Lock Notice of Allowance Mailed — Application Received in Office of Publications 2632 Aghdam, Freshteh N