Microchip Technology Incorporated Patent Portfolio Statistics

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Microchip Technology Incorporated

Profile Summary

This article summarizes the perfomance of the assignee in the recent years. The overall statistics for this portfolio help to analyze the areas where the assignee is performing well. The filing trend, perfomance across the tech centers and the perfomance of the recent applications has been mentioned below. All the stats are calculated based on the perfomance in USPTO.

How does the overall patent portfolio of Microchip Technology Incorporated look like?

Assignee Art Units
Total Applications: 4,364 1,899,343
Granted Patents: 3,959 1,254,715
Grant Index 94.67% ↑ 81.86%
Abandoned/Rejected Applications: 223 (5.33%) 278,042 (18.14%)
In-Process Applications: 175 366,586
Average Grant Time: 2.74 Years ↑ 2.66 Years
Average Office Actions: 1.59 ↑ 1.49

Which Technology Area Microchip Technology Incorporated is filing most patents in? (Last 10 years)

Art Unit Definition Total Applications
2816 Semiconductors/Memory 233
2838 Electrical Circuits and Systems 190
2824 Semiconductors/Memory 169
2827 Semiconductors/Memory 159
2819 Semiconductors/Memory 145

How many patents are Microchip Technology Incorporated filing every year?

Year Total Applications Predicted
2022 0* 227
2021 54* 198
2020 123 207
2019 105 105
2018 185 –
2017 107 –
2016 179 –
2015 136 –
2014 213 –
2013 248 –

*The drop in the number of applications filed in last two years compared to previous years is because applications can take up to 18 months to get published

Recently filed patent applications of Microchip Technology Incorporated in USPTO?

Publication number: US20220092201A1
Application number: 17/457,700

Abstract:
Systems for authenticating a file are disclosed. A system may include one or more physical devices. The one or more physical devices may select, based on an identifier, a subset of data segments of a computer file for generating a first digest with a cryptographic function. The one or more physical devices may also execute the cryptographic function on the selected subset of data segments of the computer file to generate the first digest. Further, the one or more physical devices may generate an authenticator based on the first digest and a private key. The one or more physical devices may further send the computer file, the identifier, and the authenticator to a secure node. Associated methods and non-transitory machine-readable medium are also disclosed.

Publication date: 2022-03-24
Applicant: Microchip Technology Incorporated
Inventors: Arthur Daniel Ujvari

Publication number: US20220095377A1
Application number: 17/457,358

Abstract:
Various embodiments relate to wired local area networks. A method may include detecting, at a node in a wired local area network, at least one event. A physical layer device of the network node is configured to implement a physical level collision avoidance (PLCA) sublayer. The at least one event may include at least one of an amount of data stored in a first-in-first-out (FIFO) buffer of the node being at least a threshold amount, and a received packet being a precision time protocol (PTP) packet incurring variable delay. The method may further include emulating a collision at the node in response to the at least one detected event.

Publication date: 2022-03-24
Applicant: Microchip Technology Incorporated
Inventors: Chen Dixon

Publication number: US20220179997A1
Application number: 17/457,298

Abstract:
Examples of the present disclosure relate generally to implementing higher-layer processing on time-sensitive data blocks at a physical-layer-interface device. Some examples include logic to perform operations, the operations including providing data blocks to a physical-layer-interface device. The operations may also include adding dummy data into one or more time-sensitive data blocks of the data blocks being provided to the physical-layer-interface device. A size of the dummy data corresponding to a size of higher-layer-processing data. Other example operations may include removing higher-layer-processing data from a first ingressing data block. The other operations may also include removing a portion of the first ingressing data block and adding the portion to a subsequent ingressing data block. A size of the portion corresponding to the size of integrity-detection data. The other operations may also include removing the integrity-detection data from an ingressing data block. Related methods, systems, and devices are also disclosed.

Publication date: 2022-06-09
Applicant: Microchip Technology Incorporated
Inventors: Branscomb Brian

How are Microchip Technology Incorporated’s applications performing in USPTO?

Application Number Title Status Art Unit Examiner
17/457,700 Authentication Of Files Docketed New Case – Ready for Examination OPAP Central, Docket
17/457,358 Emulating Collisions In Wired Local Area Networks And Related Systems, Methods, And Devices Docketed New Case – Ready for Examination OPAP Central, Docket
17/457,298 Higher-Layer-Processing Data In Time-Sensitive Data Blocks At A Physical-Layer-Interface Device – OPAP Central, Docket
17/457,185 Interfacing With Systems, For Processing Data Samples, And Related Systems, Methods And Apparatuses Docketed New Case – Ready for Examination OPAP Central, Docket
17/456,496 Receiver Processing Circuitry For Motion Detection And Related Systems, Methods, And Apparatuses – OPAP Central, Docket