Marvell World Trade Ltd Patent Portfolio Statistics

Marvell World Trade Ltd.

Profile Summary

This article summarizes the perfomance of the assignee in the recent years. The overall statistics for this portfolio help to analyze the areas where the assignee is performing well. The filing trend, perfomance across the tech centers and the perfomance of the recent applications has been mentioned below. All the stats are calculated based on the perfomance in USPTO.

How does the overall patent portfolio of Marvell World Trade Ltd. look like?

Assignee Art Units
Total Applications: 2,258 1,412,230
Granted Patents: 2,071 1,113,275
Grant Index 95.13% 83.0%
Abandoned/Rejected Applications: 106 (4.87%) 227,999 (17.0%)
In-Process Applications: 81 70,956
Average Grant Time: 2.59 Years 2.63 Years
Average Office Actions: 1.51 1.51

Which Technology Area Marvell World Trade Ltd. is filing most patents in? (Last 10 years)

Art Unit Definition Total Applications
2632 Digital and Optical Communications 65
2817 Semiconductors/Memory 62
2112 Computer Error Control, Reliability, & Control Systems 60
2838 Electrical Circuits and Systems 55
2631 Digital and Optical Communications 54

How many patents are Marvell World Trade Ltd. filing every year?

Year Total Applications Predicted
2022 0* 801
2021 0* 643
2020 0 639
2019 107 107
2018 100
2017 78
2016 141
2015 131
2014 274
2013 272

*The drop in the number of applications filed in last two years compared to previous years is because applications can take up to 18 months to get published

Recently filed patent applications of Marvell World Trade Ltd. in USPTO?

Publication number: US20200202894A1
Application number: 16/720,818

Methods and systems are disclosed for controlling fly-height of a read/write (RW) head. In an embodiment, a RW channel detects a servo gate signal and toggles a mode signal within a preamplifier from a RW data mode signal to a fly-height control (FHC) mode signal. In response to the FHC mode signal, the RW channel transmits FHC data over a differential interface to the preamplifier.

Publication date: 2020-06-25
Applicant: Marvell World Trade Ltd.
Inventors: Sugawara Takao

Publication number: US20200202893A1
Application number: 16/715,559

Zone self-servo write (SSW) technology is disclosed that leverages two clock signals synchronized in parallel to transition between zones to write servo patterns at different frequencies while minimizing error rate despite the different frequencies. Two separate clock signals (“clocks”) are used to locate and lock to different reference spirals. By updating both clocks in parallel instead of in series, error rate for writing while stepping up frequency across zones is reduced.

Publication date: 2020-06-25
Applicant: Marvell World Trade Ltd.
Inventors: Katchmart Supaket

Publication number: US20200118868A1
Application number: 16/713,044

A method of forming an integrated circuit includes: forming a dielectric layer, a hard mask layer, a film layer and a photoresist layer; and patterning the photoresist layer to form a via mask, where the via mask is oversized, such that the via mask extends across opposing sides of a metal line mask in the hard mask layer. The method further includes: etching the film layer and the dielectric layer based on the patterned photoresist layer; ashing the photoresist layer and the film layer; etching the dielectric layer based on a pattern of the hard mask layer to provide a via region and a metal line region; etching the hard mask layer and the dielectric layer; and performing a plurality of dual damascene process operations to form a via in the via region and a metal line in the metal line region in the integrated circuit.

Publication date: 2020-04-16
Applicant: Marvell World Trade Ltd.
Inventors: Min She

How are Marvell World Trade Ltd.’s applications performing in USPTO?

Application Number Title Status Art Unit Examiner
16/720,818 Differential Interface Transmission Of Fly-Height Control Data Patented Case 2688 Hindi, Nabil Z
16/715,559 Zone Self Servo Writing With Synchronized Parallel Clocks Patented Case 2688 Hindi, Nabil Z
16/713,044 Creating An Aligned Via And Metal Line In An Integrated Circuit Including Forming An Oversized Via Mask Patented Case 2813 Nicely, Joseph C
16/706,073 Physical Layer Protocol Data Unit Directional Transmission Patented Case 2461 Mattis, Jason E
16/703,694 Reducing Offset Of A Differential Signal Output By A Capacitive Coupling Stage Of A Hard Disk Drive Preamplifier Patented Case 2688 Hindi, Nabil Z