Marvell International Ltd Patent Portfolio Statistics

Publication number: US20210365378A1
Application number: 17/392,447

Abstract:
The size of a cache is modestly increased so that a short pointer to a predicted next memory address in the same cache is added to each cache line in the cache. In response to a cache hit, the predicted next memory address identified by the short pointer in the cache line of the hit along with an associated entry are pushed to a next faster cache when a valid short pointer to the predicted next memory address is present in the cache line of the hit.

Publication date: 2021-11-25
Applicant: Marvell International Ltd.
Inventors: Alexander Rucker

---

Publication number: US20210208928A1
Application number: 16/737,786

Abstract:
A method for handling an interrupt includes receiving, in hardware or in firmware, a request from a task executing in userspace, where the request is to assign a function in the task and state information for the task to an interrupt. The hardware or firmware records the state information for the task, and assigns defined state information for the function to an event caused by the interrupt. When the interrupt occurs, the interrupt is serviced by saving context including the state information for the task in the memory, loading the defined state information for the function into registers, running the function, and then returning to the task preempted by the interrupt.

Publication date: 2021-07-08
Applicant: Marvell International Ltd.
Inventors: Kapoor Prasun

---

Publication number: US20210192336A1
Application number: 16/724,554

Abstract:
Disclosed is a processing unit for computing a convolution of an activations matrix (e.g., a N×N activations matrix) and a weights kernel (e.g., a M×M weights kernel). The processing unit specifically employs an array of processing elements and a hardware-implemented spiral algorithm to compute the convolution. Due to this spiral algorithm, the need for a discrete data setup logic block is avoided, activation values from the activations matrix can be pre-loaded into processing elements only one time so that the need to repeatedly access the activations matrix is avoided, and the computation can be completed in a relatively low number of clock cycles, which is independent of the number of activation values in the activation matrix and which is equal to the number of weight values in a weights kernel. Also disclosed is an associated processing method.

Publication date: 2021-06-24
Applicant: Marvell International Ltd.
Inventors: Deepak Hanagandi I

---