Marvell International Ltd Patent Portfolio Statistics

Marvell International Ltd.

Profile Summary

This article summarizes the perfomance of the assignee in the recent years. The overall statistics for this portfolio help to analyze the areas where the assignee is performing well. The filing trend, perfomance across the tech centers and the perfomance of the recent applications has been mentioned below. All the stats are calculated based on the perfomance in USPTO.

How does the overall patent portfolio of Marvell International Ltd. look like?

Assignee Art Units
Total Applications: 8,253 1,525,147
Granted Patents: 7,919 1,207,722
Grant Index 98.07% 82.96%
Abandoned/Rejected Applications: 156 (1.93%) 248,069 (17.04%)
In-Process Applications: 178 69,356
Average Grant Time: 2.65 Years 2.67 Years
Average Office Actions: 1.49 1.52

Which Technology Area Marvell International Ltd. is filing most patents in? (Last 10 years)

Art Unit Definition Total Applications
2112 Computer Error Control, Reliability, & Control Systems 292
2611 Computer Graphic Processing, 3D Animation, Display Color Attribute, Object Processing, Hardware and Memory 284
2627 Selective Visual Display Systems 248
2819 Semiconductors/Memory 221
2117 Computer Error Control, Reliability, & Control Systems 217

How many patents are Marvell International Ltd. filing every year?

Year Total Applications Predicted
2022 0* 674
2021 0* 626
2020 6 510
2019 223 223
2018 228
2017 198
2016 375
2015 378
2014 669
2013 772

*The drop in the number of applications filed in last two years compared to previous years is because applications can take up to 18 months to get published

Recently filed patent applications of Marvell International Ltd. in USPTO?

Publication number: US20210365378A1
Application number: 17/392,447

The size of a cache is modestly increased so that a short pointer to a predicted next memory address in the same cache is added to each cache line in the cache. In response to a cache hit, the predicted next memory address identified by the short pointer in the cache line of the hit along with an associated entry are pushed to a next faster cache when a valid short pointer to the predicted next memory address is present in the cache line of the hit.

Publication date: 2021-11-25
Applicant: Marvell International Ltd.
Inventors: Alexander Rucker

Publication number: US20210208928A1
Application number: 16/737,786

A method for handling an interrupt includes receiving, in hardware or in firmware, a request from a task executing in userspace, where the request is to assign a function in the task and state information for the task to an interrupt. The hardware or firmware records the state information for the task, and assigns defined state information for the function to an event caused by the interrupt. When the interrupt occurs, the interrupt is serviced by saving context including the state information for the task in the memory, loading the defined state information for the function into registers, running the function, and then returning to the task preempted by the interrupt.

Publication date: 2021-07-08
Applicant: Marvell International Ltd.
Inventors: Kapoor Prasun

Publication number: US20210192336A1
Application number: 16/724,554

Disclosed is a processing unit for computing a convolution of an activations matrix (e.g., a N×N activations matrix) and a weights kernel (e.g., a M×M weights kernel). The processing unit specifically employs an array of processing elements and a hardware-implemented spiral algorithm to compute the convolution. Due to this spiral algorithm, the need for a discrete data setup logic block is avoided, activation values from the activations matrix can be pre-loaded into processing elements only one time so that the need to repeatedly access the activations matrix is avoided, and the computation can be completed in a relatively low number of clock cycles, which is independent of the number of activation values in the activation matrix and which is equal to the number of weight values in a weights kernel. Also disclosed is an associated processing method.

Publication date: 2021-06-24
Applicant: Marvell International Ltd.
Inventors: Deepak Hanagandi I

How are Marvell International Ltd.’s applications performing in USPTO?

Application Number Title Status Art Unit Examiner
17/392,447 Method Of Cache Prefetching That Increases The Hit Rate Of A Next Faster Cache Docketed New Case – Ready for Examination OPAP Central, Docket
16/737,786 Interrupt Servicing In Userspace Patented Case 2181 Taylor, Brooke Jazmond
16/724,554 Processing Unit And Method For Computing A Convolution Using A Hardware-Implemented Spiral Algorithm Docketed New Case – Ready for Examination 2181 Abad, Farley J
15/929,191 Adc-Based Serdes With Sub-Sampled Adc For Eye Monitoring Patented Case 2632 Aghdam, Freshteh N
16/702,983 Balanced Current Mirrors For Biasing A Magnetic Resistor In A Hard Disk Drive Patented Case 2688 Hindi, Nabil Z