International Business Machines Corporation Patent Portfolio Statistics

International Business Machines Corporation

Profile Summary

This article summarizes the perfomance of the assignee in the recent years. The overall statistics for this portfolio help to analyze the areas where the assignee is performing well. The filing trend, perfomance across the tech centers and the perfomance of the recent applications has been mentioned below. All the stats are calculated based on the perfomance in USPTO.

How does the overall patent portfolio of International Business Machines Corporation look like?

Assignee Art Units
Total Applications: 155,109 1,539,102
Granted Patents: 127,295 950,810
Grant Index 86.13% 80.74%
Abandoned/Rejected Applications: 20,504 (13.87%) 226,859 (19.26%)
In-Process Applications: 7,019 361,433
Average Grant Time: 3.01 Years 2.75 Years
Average Office Actions: 1.75 1.63

Which Technology Area International Business Machines Corporation is filing most patents in? (Last 10 years)

Art Unit Definition Total Applications
2113 Computer Error Control, Reliability, & Control Systems 1,941
2114 Computer Error Control, Reliability, & Control Systems 1,831
2825 Semiconductors/Memory 1,793
2191 Interprocess Communication and Software Development 1,683
2183 Computer Architecture and I/O 1,678

How many patents are International Business Machines Corporation filing every year?

Year Total Applications
2022 0*
2021 526*
2020 4,414
2019 9,188
2018 8,355
2017 11,181
2016 10,563
2015 10,824
2014 7,383
2013 8,700

*The drop in the number of applications filed in last two years compared to previous years is because applications can take up to 18 months to get published

Recently filed patent applications of International Business Machines Corporation in USPTO?

Publication number: US20220108923A1
Application number: 17/553,950

Abstract:
Partial self-aligned contact structures are provided. In one aspect, a method of forming a semiconductor device includes: patterning fins in a substrate; forming a gate(s) over the fins, separated from source/drains by first spacers, wherein a lower portion of the gate(s) includes a workfunction-setting metal, and an upper portion of the gate(s) includes a core metal between a metal liner; recessing the metal liner to form divots in the upper portion of the gate(s) in between the first spacers and the core metal; forming second spacers in the divots such that the first spacers and the second spacers surround the core metal in the upper portion of the gate(s); forming lower source/drain contacts in between the first spacers over the source/drains; recessing the lower source/drain contacts to form gaps over the lower source/drain contacts; and forming source/drain caps in the gaps. A semiconductor device is also provided.

Publication date: 2022-04-07
Applicant: International Business Machines Corporation
Inventors: Ruilong Xie


Publication number: US20220108015A1
Application number: 17/552,726

Abstract:
A method includes: federating, by a computer device, a proxy hardware security module from a physical hardware security module; storing, by the computer device, the proxy hardware security module; receiving, by the computer device, a first one of a plurality of periodic identifying communications from the physical hardware security module; and erasing, by the computer device, the proxy hardware security module as a result of the computer device not receiving a second one of the plurality of periodic identifying communications.

Publication date: 2022-04-07
Applicant: International Business Machines Corporation
Inventors: Marco Pavone


Publication number: US20220108922A1
Application number: 17/551,531

Abstract:
A method of forming fully aligned top vias is provided. The method includes forming a fill layer on a conductive line, wherein the fill layer is adjacent to one or more vias. The method further includes forming a spacer layer selectively on the exposed surface of the fill layer, wherein the top surface of the one or more vias is exposed after forming the spacer layer. The method further includes depositing an etch-stop layer on the exposed surfaces of the spacer layer and the one or more vias, and forming a cover layer on the etch-stop layer.

Publication date: 2022-04-07
Applicant: International Business Machines Corporation
Inventors: Christopher J Penny


How are International Business Machines Corporation’s applications performing in USPTO?

Application Number Title Status Art Unit Examiner
17/553,950 Partial Self-Aligned Contact For Mol Docketed New Case – Ready for Examination OPAP Central, Docket
17/552,726 Hsm Self-Destruction In A Hybrid Cloud Kms Solution Docketed New Case – Ready for Examination OPAP Central, Docket
17/551,531 Fully Aligned Top Vias Docketed New Case – Ready for Examination OPAP Central, Docket
17/552,027 Pillar-Based Memory Hardmask Smoothing And Stress Reduction Docketed New Case – Ready for Examination OPAP Central, Docket
17/550,121 Creation Of A Summary For A Plurality Of Texts Docketed New Case – Ready for Examination OPAP Central, Docket