Infineon Technologies Austria Ag Patent Portfolio Statistics

Infineon Technologies Austria Ag

Profile Summary

This article summarizes the perfomance of the assignee in the recent years. The overall statistics for this portfolio help to analyze the areas where the assignee is performing well. The filing trend, perfomance across the tech centers and the perfomance of the recent applications has been mentioned below. All the stats are calculated based on the perfomance in USPTO.

How does the overall patent portfolio of Infineon Technologies Austria Ag look like?

Total Applications: 2,024
Granted Patents: 1,698
Grant Index 91.09 %
Abandoned/Rejected Applications: 166 (8.91%)
In-Process Applications: 149
Average Grant Time: 2.48 Years
Average Office Actions: 1.6

Which Technology Area Infineon Technologies Austria Ag is filing most patents in? (Last 10 years)

Art Unit Definition Total Applications
2838 Electrical Circuits and Systems 355
2842 Electrical Circuits and Systems 131
2815 Semiconductors/Memory 85
2814 Semiconductors/Memory 68
2811 Semiconductors/Memory 66

How many patents are Infineon Technologies Austria Ag filing every year?

Year Total Applications
2022 0*
2021 50*
2020 127
2019 124
2018 143

*The drop in the number of applications filed in last two years compared to previous years is because applications can take up to 18 months to get published

Recently filed patent applications of Infineon Technologies Austria Ag in USPTO?

Publication number: US20220029013A1
Application number: 17/494,098

Abstract:
A method for fabricating a semiconductor device includes: forming a trench in a first major surface of a semiconductor body having a first conductivity type; forming a gate in the trench; forming a body region of a second conductivity type in the semiconductor body; implanting a second dopant species into a first region of the body region and a first dopant species into a second region of the body region, the first dopant species providing the first conductivity type, the second dopant species being different from the first dopant species and reducing the diffusion of the first dopant species in the semiconductor body; and thermally annealing the semiconductor body to form a source region that includes the first and second dopant species, and to produce a pn-junction between the source and body regions at a depth dpn from the first major surface, wherein 50 nm<dpn<300 nm.

Publication date: 2022-01-27
Applicant: Infineon Technologies Austria Ag
Inventors: Georg Johannes Laven


Publication number: US20220013665A1
Application number: 17/482,490

Abstract:
A vertical power semiconductor transistor device includes: a drain region of a first conductivity type; a body region of a second conductivity type; a drift region of the first conductivity type which separates the body region from the drain region; a source region of the first conductivity type separated from the drift region by the body region; a gate trench extending through the source and body regions and into the drift region, the gate trench including a gate electrode; and a field electrode in the gate trench or in a separate trench. The drift region has a generally linearly graded first doping profile which increases from the body region toward a bottom of the trench that includes the field electrode, and a graded second doping profile that increases at a greater rate than the first doping profile from an end of the first doping profile toward the drain region.

Publication date: 2022-01-13
Applicant: Infineon Technologies Austria Ag
Inventors: Cdric Ouvrard


Publication number: US20220007512A1
Application number: 17/475,429

Abstract:
An interposer for a processor includes: an electrically insulating material having a first main side and a second main side opposite the first main side; an electrical interface for a processor substrate at the first main side of the electrically insulating material; and a power device module embedded in the electrically insulating material and configured to convert a voltage provided at the second main side of the electrically insulating material to a lower voltage. The power device module has at least one contact configured to receive the voltage provided at the second main side of the electrically insulating material. Distribution circuitry embedded in the electrically insulating material is configured to carry the lower voltage provided by the power device module to the first main side of the electrically insulating material.

Publication date: 2022-01-06
Applicant: Infineon Technologies Austria Ag
Inventors: Clavette Danny


How are Infineon Technologies Austria Ag’s applications performing in USPTO?

Application Number Title Status Art Unit Examiner
17/494,098 Method For Manufacturing A Semiconductor Device OPAP Central, Docket
17/482,490 Mosfet Having A Drift Region With A Graded Doping Profile And Methods Of Manufacturing Thereof OPAP Central, Docket
17/475,429 Processor Interposer And Electronic System Including The Processor Interposer Docketed New Case – Ready for Examination OPAP Central, Docket
17/473,539 Electric Power Converter Docketed New Case – Ready for Examination OPAP Central, Docket
17/470,635 Power Relay Circuit Docketed New Case – Ready for Examination OPAP Central, Docket