Industrial Technology Research Institute Patent Portfolio Statistics

Industrial Technology Research Institute

Profile Summary

This article summarizes the perfomance of the assignee in the recent years. The overall statistics for this portfolio help to analyze the areas where the assignee is performing well. The filing trend, perfomance across the tech centers and the perfomance of the recent applications has been mentioned below. All the stats are calculated based on the perfomance in USPTO.

How does the overall patent portfolio of Industrial Technology Research Institute look like?

Total Applications: 10,540
Granted Patents: 7,384
Grant Index 72.83 %
Abandoned/Rejected Applications: 2,754 (27.17%)
In-Process Applications: 388
Average Grant Time: 2.72 Years
Average Office Actions: 1.34

Which Technology Area Industrial Technology Research Institute is filing most patents in? (Last 10 years)

Art Unit Definition Total Applications
2871 Optics 194
2872 Optics 124
Opap Parked GAU 120
2817 Semiconductors/Memory 99
2816 Semiconductors/Memory 97

How many patents are Industrial Technology Research Institute filing every year?

Year Total Applications
2022 0*
2021 46*
2020 234
2019 320
2018 362

*The drop in the number of applications filed in last two years compared to previous years is because applications can take up to 18 months to get published

Recently filed patent applications of Industrial Technology Research Institute in USPTO?

Publication number: US20210409911A1
Application number: 17/471,706

Abstract:
A grouping method of user devices comprises configuring one or more codes for each of the user devices by a base station wherein each of said one or more codes corresponds to a delay tolerance, performing a grouping task by the base station according to the delay tolerances and a determining result of channel-usage demand corresponding to each of the user devices so as to form one or more first-type groups and one or more second-type groups wherein each first-type group corresponds to a first-group delay tolerance and each second-type group corresponds to a second-group delay tolerance, and performing a selection from user devices in the first-type groups and the second-type groups to form one or more target groups by the base station according to the first-group delay tolerances and the second-group delay tolerances.

Publication date: 2021-12-30
Applicant: Industrial Technology Research Institute
Inventors: Huang Jen-Feng


Publication number: US20210380404A1
Application number: 17/412,160

Abstract:
A MEMS device is provided. The MEMS device includes a substrate having at least one contact, a first dielectric layer disposed on the substrate, at least one metal layer disposed on the first dielectric layer, a second dielectric layer disposed on the first dielectric layer and the metal layer and having a recess structure, and a structure layer disposed on the second dielectric layer and having an opening. The opening is disposed on and corresponds to the recess structure, and the cross-sectional area at the bottom of the opening is smaller than the cross-sectional area at the top of the recess structure. The MEMS device also includes a sealing layer, and at least a portion of the sealing layer is disposed in the opening and the recess structure. The second dielectric layer, the structure layer, and the sealing layer define a chamber.

Publication date: 2021-12-09
Applicant: Industrial Technology Research Institute
Inventors: Jing-Yuan Lin


Publication number: US20210375982A1
Application number: 17/385,954

Abstract:
A display array including a semiconductor stacked layer, an insulating layer, a plurality of electrode pads, and a driving backplane is provided. The semiconductor stacked layer has a plurality of light emitting regions arranged along a reference plane. The insulating layer is disposed to an outer surface of the semiconductor stacked layer and contacts the semiconductor stacked layer. The insulating layer has a plurality of openings respectively corresponding to the plurality of light emitting regions. The electrode pads are disposed to the insulating layer and are respectively electrically connect the plurality of light emitting regions through the plurality of openings. The driving backplane is disposed to the semiconductor stacked layer and electrically connected to the plurality of electrode pads, wherein a light emitting material layer of the semiconductor stacked layer has consistency along an extension direction of the reference plane.

Publication date: 2021-12-02
Applicant: Industrial Technology Research Institute
Inventors: Chao Chia-Hsin


How are Industrial Technology Research Institute’s applications performing in USPTO?

Application Number Title Status Art Unit Examiner
17/471,706 Method Of Grouping User Devices Docketed New Case – Ready for Examination OPAP Central, Docket
17/412,160 Mems Device, Manufacturing Method Of The Same, And Integrated Mems Module Using The Same Docketed New Case – Ready for Examination OPAP Central, Docket
17/385,954 Display Array Docketed New Case – Ready for Examination OPAP Central, Docket
17/371,142 Field-Effect Transistor And Method For Manufacturing The Same Docketed New Case – Ready for Examination OPAP Central, Docket
17/369,669 Method And System For Simultaneously Tracking 6 Dof Poses Of Movable Object And Movable Camera OPAP Central, Docket