Fuji Electric Co., Ltd Patent Portfolio Statistics

Fuji Electric Co., Ltd.

Profile Summary

This article summarizes the perfomance of the assignee in the recent years. The overall statistics for this portfolio help to analyze the areas where the assignee is performing well. The filing trend, perfomance across the tech centers and the perfomance of the recent applications has been mentioned below. All the stats are calculated based on the perfomance in USPTO.

How does the overall patent portfolio of Fuji Electric Co., Ltd. look like?

Total Applications: 4,036
Granted Patents: 3,316
Grant Index 90.08 %
Abandoned/Rejected Applications: 365 (9.92%)
In-Process Applications: 329
Average Grant Time: 2.18 Years
Average Office Actions: 1.25

Which Technology Area Fuji Electric Co., Ltd. is filing most patents in? (Last 10 years)

Art Unit Definition Total Applications
2838 Electrical Circuits and Systems 375
2823 Semiconductors/Memory 175
2842 Electrical Circuits and Systems 157
Opap Parked GAU 152
2836 Electrical Circuits and Systems 121

How many patents are Fuji Electric Co., Ltd. filing every year?

Year Total Applications
2022 0*
2021 194*
2020 272
2019 245
2018 319

*The drop in the number of applications filed in last two years compared to previous years is because applications can take up to 18 months to get published

Recently filed patent applications of Fuji Electric Co., Ltd. in USPTO?

Publication number: US20220028735A1
Application number: 17/496,360

Abstract:
In a contact hole of an interlayer insulating film, a tungsten film forming a contact plug is embedded via a barrier metal. The interlayer insulating film is formed by sequentially stacked HTO and BPSG films. The BPSG film has an etching rate faster than that of the HTO film with respect to a hydrofluoric acid solution used in wet etching of preprocessing before formation of the barrier metal. After the contact hole is formed in the interlayer insulating film, a width of an upper portion of the contact hole at the BPSG film is increased in a step-like shape, to be wider than a width of a lower portion at the HTO film by the wet etching before the formation of the barrier metal, whereby an aspect ratio of the contact hole is reduced. Thus, size reductions and enhancement of the reliability may be realized.

Publication date: 2022-01-27
Applicant: Fuji Electric Co., Ltd.
Inventors: Suzawa Takaaki


Publication number: US20220013368A1
Application number: 17/486,977

Abstract:
Provided is a semiconductor device, including a semiconductor substrate having an upper surface and a lower surface and including a bulk donor, wherein a hydrogen chemical concentration distribution of the semiconductor substrate in a depth direction is flat, monotonically increasing, or monotonically decreasing from the lower surface to the upper surface except for a portion where a local hydrogen concentration peak is provided; and a donor concentration of the semiconductor substrate is higher than a bulk donor concentration over an entire region from the upper surface to the lower surface. Hydrogen ions may be irradiated from the upper surface or the lower surface of the semiconductor substrate so as to penetrate the semiconductor substrate in the depth direction.

Publication date: 2022-01-13
Applicant: Fuji Electric Co., Ltd.
Inventors: Hiroshi Takishita


Publication number: US20220013635A1
Application number: 17/486,984

Abstract:
Provided is a semiconductor device including: a semiconductor substrate including a bulk donor; and a first buffer region of a first conductivity type, the first buffer region being provided on a lower surface side of the semiconductor substrate and having one or more doping concentration peaks and one or more hydrogen concentration peaks in a depth direction of the semiconductor substrate, in which a doping concentration at a shallowest concentration peak, out of the doping concentration peaks of the first buffer region, closest to the lower surface of the semiconductor substrate is 50 times as high as a concentration of the bulk donor of the semiconductor substrate or lower. The doping concentration at the shallowest concentration peak may be lower than a reference carrier concentration obtained when current that is 1/10 of rated current flows between an upper surface and the lower surface of the semiconductor substrate.

Publication date: 2022-01-13
Applicant: Fuji Electric Co., Ltd.
Inventors: Tamura Takahiro


How are Fuji Electric Co., Ltd.’s applications performing in USPTO?

Application Number Title Status Art Unit Examiner
17/496,360 Semiconductor Device And Method Of Manufacturing Semiconductor Device OPAP Central, Docket
17/486,977 Semiconductor Device And Manufacturing Method Of Semiconductor Device OPAP Central, Docket
17/486,984 Semiconductor Device And Manufacturing Method For Semiconductor Device OPAP Central, Docket
17/487,563 Insulated-Gate Semiconductor Device OPAP Central, Docket
17/486,968 Semiconductor Device And Manufacturing Method Of Semiconductor Device OPAP Central, Docket