Freescale Semiconductor, Inc Patent Portfolio Statistics

Freescale Semiconductor, Inc.

Profile Summary

This article summarizes the perfomance of the assignee in the recent years. The overall statistics for this portfolio help to analyze the areas where the assignee is performing well. The filing trend, perfomance across the tech centers and the perfomance of the recent applications has been mentioned below. All the stats are calculated based on the perfomance in USPTO.

How does the overall patent portfolio of Freescale Semiconductor, Inc. look like?

Total Applications: 10,565
Granted Patents: 9,547
Grant Index 91.05 %
Abandoned/Rejected Applications: 938 (8.95%)
In-Process Applications: 80
Average Grant Time: 2.59 Years
Average Office Actions: 1.33

Which Technology Area Freescale Semiconductor, Inc. is filing most patents in? (Last 10 years)

Art Unit Definition Total Applications
2818 Semiconductors/Memory 379
2816 Semiconductors/Memory 365
2842 Electrical Circuits and Systems 362
2812 Semiconductors/Memory 293
2817 Semiconductors/Memory 257

How many patents are Freescale Semiconductor, Inc. filing every year?

Year Total Applications
2022 0*
2021 0*
2020 6
2019 8
2018 14

*The drop in the number of applications filed in last two years compared to previous years is because applications can take up to 18 months to get published

Recently filed patent applications of Freescale Semiconductor, Inc. in USPTO?

Publication number:
Application number: 15/688,029


Publication date:
Applicant: Freescale Semiconductor, Inc.
Inventors: Arvinte Marius Octavian

Publication number: US20180323836A1
Application number: 15/668,345

A receiver decodes received data streams based on a subset of candidate decoding constellation points. A first stage of a decoder of the receiver selects a subset of candidate decoding constellation points by identifying a decoded value for an initial data stream of the set of data streams. A second stage then applies MMSE error detection to each of the constellation points in the selected subset, and calculates an error metric based on the MMSE error detection results. The decoder selects the constellation points having the lowest error metrics, and uses the selected constellation points as an initial set of points for decoding the next data stream to be decoded.

Publication date: 2018-11-08
Applicant: Freescale Semiconductor, Inc.
Inventors: Arvinte Marius Octavian

Publication number: US20170373053A1
Application number: 15/344,131

An ESD protection structure formed within a semiconductor substrate of an integrated circuit device. The ESD protection structure comprises a thyristor structure being formed from a first P-doped section forming an anode of the thyristor structure, a first N-doped section forming a collector node of the thyristor structure, a second P-doped section, and a second N-doped section forming a cathode of the thyristor structure. A low-resistance coupling is provided between an upper surface region of the collector node of the thyristor structure and the anode of the thyristor structure.

Publication date: 2017-12-28
Applicant: Freescale Semiconductor, Inc.
Inventors: Changsoo Hong

How are Freescale Semiconductor, Inc.’s applications performing in USPTO?

Application Number Title Status Art Unit Examiner
15/688,029 Transmitter Precoding Based On Quality Score Patented Case 2631 Kim, Kevin
15/668,345 Complexity Reduction For Receiver Decoding Patented Case 2633 Corrielus, Jean B
15/344,131 Esd Protection Structure Patented Case 2897 Hall, Victoria Kathleen
15/344,250 Wireless Power Transmitters With Wide Input Voltage Range And Methods Of Their Operation Patented Case 2851 Ngo, Brian
15/344,304 Phase Shift And Attenuation Circuits For Use With Multiple-Path Amplifiers Patented Case 2842 Almo, Khareem E