Empire Technology Development Llc Patent Portfolio Statistics

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Empire Technology Development Llc

Profile Summary

This article summarizes the perfomance of the assignee in the recent years. The overall statistics for this portfolio help to analyze the areas where the assignee is performing well. The filing trend, perfomance across the tech centers and the perfomance of the recent applications has been mentioned below. All the stats are calculated based on the perfomance in USPTO.

How does the overall patent portfolio of Empire Technology Development Llc look like?

Assignee Art Units
Total Applications: 3,151 1,630,840
Granted Patents: 2,573 1,194,780
Grant Index 81.86% ↑ 77.38%
Abandoned/Rejected Applications: 570 (18.14%) 349,285 (22.62%)
In-Process Applications: 8 86,775
Average Grant Time: 2.83 Years ↑ 2.69 Years
Average Office Actions: 1.7 ↑ 1.57

Which Technology Area Empire Technology Development Llc is filing most patents in? (Last 10 years)

Art Unit Definition Total Applications
3714 Amusement and Education Devices 40
1759 Fuel Cells, Batteries, Solar Cells, ElectroChemistry, Radiation Imagery 31
2195 Interprocess Communication and Software Development 30
1765 Oraganic Chemistry, Polymers, Compositions 29
1736 Metallurgy, Metal Working, Inorganic Chemistry, Catalyst, Electrophotography, Photolithography 27

How many patents are Empire Technology Development Llc filing every year?

Year Total Applications Predicted
2022 0* 121
2021 0* 167
2020 1 54
2019 14 14
2018 32 –
2017 110 –
2016 271 –
2015 396 –
2014 426 –
2013 478 –

*The drop in the number of applications filed in last two years compared to previous years is because applications can take up to 18 months to get published

Recently filed patent applications of Empire Technology Development Llc in USPTO?

Publication number: US20190370175A1
Application number: 16/448,239

Abstract:
Techniques described herein generally include methods and systems related to cache partitioning in a chip multiprocessor. Cache-partitioning for a single thread or application between multiple data sources improves energy or latency efficiency of a chip multiprocessor by exploiting variations in energy cost and latency cost of the multiple data sources. Partition sizes for each data source may be selected using an optimization algorithm that minimizes or otherwise reduces latencies or energy consumption associated with cache misses.

Publication date: 2019-12-05
Applicant: Empire Technology Development Llc
Inventors: Solihin Yan

Publication number: US20190342876A1
Application number: 16/419,847

Abstract:
Technologies and implementations for wireless communication in a wireless network including transmitting downlink information on a first frequency channel to Frequency Division Duplexing (FDD) User Equipments (UEs), transmitting downlink information on a second frequency channel during downlink portions of Time Domain Duplex (TDD) frame periods of the second frequency channel to TDD UEs, wherein the second frequency channel is the same as the frequency channel on which the FDD UEs are configured to transmit, and controlling uplink transmissions from the FDD UEs to occur only during uplink portions of TDD frame periods of the second frequency channel.

Publication date: 2019-11-07
Applicant: Empire Technology Development Llc
Inventors: Drucker Elliott H

Publication number: US20190280967A1
Application number: 16/354,247

Abstract:
A hierarchical wireless network is provided with a mesh backbone network portion and a switching tree network portion. The mesh backbone network portion includes first tier nodes each having at least one wireless link to another first tier node. The first tier nodes execute a link-state protocol for routing packets. The switching tree network portion includes second tier nodes each having a single wireless link to one first tier node and at least one wireless link to one third tier node, and third tier nodes each having a single wireless link to one second tier node. The second tier and the third tier nodes execute switching rules for switching packets.

Publication date: 2019-09-12
Applicant: Empire Technology Development Llc
Inventors: Chiang Mung

How are Empire Technology Development Llc’s applications performing in USPTO?

Application Number Title Status Art Unit Examiner
16/448,239 Cache Partitioning In A Multicore Processor Patented Case 2138 Portka, Gary J
16/419,847 Hybrid Fdd/Tdd Wireless Network Patented Case 2472 Musa, Abdelnabi O
16/354,247 Wireless Home Network Routing Protocol Patented Case 2474 Elliott Iv, Benjamin H
16/354,246 Intermediary Graphics Rendition Patented Case 3715 Renwick, Reginald A
16/299,038 Coordination Of Multiple Structured Light-Based 3D Image Detectors Final Rejection Mailed 2423 Hallenbeck-Huber, Jeremiah Charles