Cypress Semiconductor Corporation Patent Portfolio Statistics

Publication number: US20140264552A1
Application number: 13/795,036

Abstract:
A memory cell can include at least a first programmable section coupled between a supply node and a first data node; a volatile storage circuit coupled to the first data node; and the programmable section includes a programmable transistor having a first source/drain (S/D) region shared with a first transistor, and a second S/D region shared with a second transistor; wherein the first S/D region has a different dopant diffusion profile than the second S/D region, and the programmable transistor has a charge storage structure formed between its control gate and its channel. Methods of forming such a memory cell are also disclosed.

Publication date: 2014-09-18
Applicant: Cypress Semiconductor Corporation
Inventors: Kaveh Shakeri

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Publication number: US20140219018A1
Application number: 13/761,217

Abstract:
A non-volatile memory device comprising a memory cell array including memory cells distributed among a plurality of sectors; a controller operable to program, read, and erase memory cells in said memory array, said controller further operable to generate and store EPLI values for programming a number of EPLI bits in one of said plurality of sectors with said stored EPLI values; and a comparator to compare said stored EPLI values with EPLI values programmed in said EPLI bits.

Publication date: 2014-08-07
Applicant: Cypress Semiconductor Corporation
Inventors: Ifat Kalderon Nitzan

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