Cree, Inc Patent Portfolio Statistics

Cree, Inc.

Profile Summary

This article summarizes the perfomance of the assignee in the recent years. The overall statistics for this portfolio help to analyze the areas where the assignee is performing well. The filing trend, perfomance across the tech centers and the perfomance of the recent applications has been mentioned below. All the stats are calculated based on the perfomance in USPTO.

How does the overall patent portfolio of Cree, Inc. look like?

Total Applications: 2,515
Granted Patents: 2,227
Grant Index 94.89 %
Abandoned/Rejected Applications: 120 (5.11%)
In-Process Applications: 167
Average Grant Time: 3.42 Years
Average Office Actions: 2.78

Which Technology Area Cree, Inc. is filing most patents in? (Last 10 years)

Art Unit Definition Total Applications
2875 Optics 432
2844 Electrical Circuits and Systems 210
2879 Optics 124
2818 Semiconductors/Memory 104
2826 Semiconductors/Memory 99

How many patents are Cree, Inc. filing every year?

Year Total Applications
2022 0*
2021 23*
2020 107
2019 91
2018 75

*The drop in the number of applications filed in last two years compared to previous years is because applications can take up to 18 months to get published

Recently filed patent applications of Cree, Inc. in USPTO?

Publication number: US20220028821A1
Application number: 17/494,909

A semiconductor device package includes a package substrate having a die attach region, a silicon carbide (SiC) substrate having a first surface including a semiconductor device layer thereon and a second surface that is opposite the first surface, and a die attach metal stack. The die attach metal stack includes a sputtered die attach material layer that attaches the second surface of the SiC substrate to the die attach region of the package substrate, where the sputtered die attach material layer comprises a void percent of about 15% or less. The sputtered die attach material layer may be formed using a sputter gas including at least one of krypton (Kr), xenon (Xe), or radon (Rn). The die attach metal stack may further include a metal interlayer that prevent contacts with a first barrier metal layer during a phase transition of the die attach material layer.

Publication date: 2022-01-27
Applicant: Cree, Inc.
Inventors: Kevin Schneider

Publication number: US20220020874A1
Application number: 17/492,032

A transistor device includes a plurality of gate fingers that extend in a first direction and are spaced apart from each other in a second direction, each of the gate fingers comprising at least spaced-apart and generally collinear first and second gate finger segments that are electrically connected to each other. The first gate finger segments are separated from the second gate finger segments in the first direction by a gap region that extends in the second direction. A resistor is disposed in the gap region.

Publication date: 2022-01-20
Applicant: Cree, Inc.
Inventors: Simon Wood

Publication number:
Application number: 17/426,669


Publication date:
Applicant: Cree, Inc.
Inventors: Kumar S Vikram

How are Cree, Inc.’s applications performing in USPTO?

Application Number Title Status Art Unit Examiner
17/494,909 Contact And Die Attach Metallization For Silicon Carbide Based Devices And Related Methods Of Sputtering Eutectic Alloys OPAP Central, Docket
17/492,032 Bypassed Gate Transistors Having Improved Stability OPAP Central, Docket
17/426,669 Compositions And Methods For Inhibiting Inosine Monophosphate Dehydrogenase Sent to Classification contractor OPAP Central, Docket
17/426,670 Compositions And Methods For Inhibiting Inosine Monophosphate Dehydrogenase Sent to Classification contractor OPAP Central, Docket
17/379,420 Radio Frequency Transistor Amplifiers And Other Multi-Cell Transistors Having Isolation Structures Docketed New Case – Ready for Examination OPAP Central, Docket