Advanced Micro Devices, Inc Patent Portfolio Statistics

Publication number: US20220027162A1
Application number: 17/497,572

Abstract:
Systems, apparatuses, and methods for compressing multiple instruction operations together into a single retire queue entry are disclosed. A processor includes at least a scheduler, a retire queue, one or more execution units, and control logic. When the control logic detects a given instruction operation being dispatched by the scheduler to an execution unit, the control logic determines if the given instruction operation meets one or more conditions for being compressed with one or more other instruction operations into a single retire queue entry. If the one or more conditions are met, two or more instruction operations are stored together in a single retire queue entry. By compressing multiple instruction operations together into an individual retire queue entry, the retire queue is able to be used more efficiently, and the processor can speculatively execute more instructions without the retire queue exhausting its supply of available entries.

Publication date: 2022-01-27
Applicant: Advanced Micro Devices, Inc.
Inventors: Kai Troester

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Publication number: US20220029954A1
Application number: 17/496,256

Abstract:
A controller assigns variable length addresses to addressable elements that are connected to a network. The variable length addresses are determined based on probabilities that packets are addressed to the corresponding addressable element. The controller transmits, to the addressable elements via the network, a routing table indicating the variable length addresses assigned to the addressable elements. Routers or addressable elements receive the routing table and route one or more packets over the network to an addressable element using variable length addresses included in a header of the one or more packets.

Publication date: 2022-01-27
Applicant: Advanced Micro Devices, Inc.
Inventors: A David Roberts

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Publication number: US20220012933A1
Application number: 17/483,678

Abstract:
Techniques for performing shader operations are provided. The techniques include, performing pixel shading at a shading rate defined by pixel shader variable rate shading (“VRS”) data, and updating the pixel VRS data that indicates one or more shading rates for one or more tiles based on whether the tiles of the one or more tiles include triangle edges or do not include triangle edges, to generate updated VRS data.

Publication date: 2022-01-13
Applicant: Advanced Micro Devices, Inc.
Inventors: Ruijin Wu

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