Advanced Micro Devices, Inc Patent Portfolio Statistics

Advanced Micro Devices, Inc.

Profile Summary

This article summarizes the perfomance of the assignee in the recent years. The overall statistics for this portfolio help to analyze the areas where the assignee is performing well. The filing trend, perfomance across the tech centers and the perfomance of the recent applications has been mentioned below. All the stats are calculated based on the perfomance in USPTO.

How does the overall patent portfolio of Advanced Micro Devices, Inc. look like?

Total Applications: 11,932
Granted Patents: 10,348
Grant Index 90.63 %
Abandoned/Rejected Applications: 1,070 (9.37%)
In-Process Applications: 509
Average Grant Time: 2.78 Years
Average Office Actions: 1.63

Which Technology Area Advanced Micro Devices, Inc. is filing most patents in? (Last 10 years)

Art Unit Definition Total Applications
2818 Semiconductors/Memory 688
2812 Semiconductors/Memory 648
2813 Semiconductors/Memory 534
2823 Semiconductors/Memory 397
2814 Semiconductors/Memory 350

How many patents are Advanced Micro Devices, Inc. filing every year?

Year Total Applications
2022 0*
2021 35*
2020 188
2019 250
2018 234

*The drop in the number of applications filed in last two years compared to previous years is because applications can take up to 18 months to get published

Recently filed patent applications of Advanced Micro Devices, Inc. in USPTO?

Publication number: US20220027162A1
Application number: 17/497,572

Systems, apparatuses, and methods for compressing multiple instruction operations together into a single retire queue entry are disclosed. A processor includes at least a scheduler, a retire queue, one or more execution units, and control logic. When the control logic detects a given instruction operation being dispatched by the scheduler to an execution unit, the control logic determines if the given instruction operation meets one or more conditions for being compressed with one or more other instruction operations into a single retire queue entry. If the one or more conditions are met, two or more instruction operations are stored together in a single retire queue entry. By compressing multiple instruction operations together into an individual retire queue entry, the retire queue is able to be used more efficiently, and the processor can speculatively execute more instructions without the retire queue exhausting its supply of available entries.

Publication date: 2022-01-27
Applicant: Advanced Micro Devices, Inc.
Inventors: Kai Troester

Publication number: US20220029954A1
Application number: 17/496,256

A controller assigns variable length addresses to addressable elements that are connected to a network. The variable length addresses are determined based on probabilities that packets are addressed to the corresponding addressable element. The controller transmits, to the addressable elements via the network, a routing table indicating the variable length addresses assigned to the addressable elements. Routers or addressable elements receive the routing table and route one or more packets over the network to an addressable element using variable length addresses included in a header of the one or more packets.

Publication date: 2022-01-27
Applicant: Advanced Micro Devices, Inc.
Inventors: A David Roberts

Publication number: US20220012933A1
Application number: 17/483,678

Techniques for performing shader operations are provided. The techniques include, performing pixel shading at a shading rate defined by pixel shader variable rate shading (“VRS”) data, and updating the pixel VRS data that indicates one or more shading rates for one or more tiles based on whether the tiles of the one or more tiles include triangle edges or do not include triangle edges, to generate updated VRS data.

Publication date: 2022-01-13
Applicant: Advanced Micro Devices, Inc.
Inventors: Ruijin Wu

How are Advanced Micro Devices, Inc.’s applications performing in USPTO?

Application Number Title Status Art Unit Examiner
17/497,572 Retire Queue Compression OPAP Central, Docket
17/496,256 Assigning Variable Length Address Identifiers To Packets In A Processing System OPAP Central, Docket
17/483,678 Vrs Rate Feedback OPAP Central, Docket
17/473,039 Metal Zero Power Ground Stub Route To Reduce Cell Area And Improve Cell Placement At The Chip Level Docketed New Case – Ready for Examination OPAP Central, Docket
17/472,977 Region Based Directory Scheme To Adapt To Large Cache Sizes Docketed New Case – Ready for Examination OPAP Central, Docket