Advanced Micro Devices, Inc Patent Portfolio Statistics

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Advanced Micro Devices, Inc.

Profile Summary

This article summarizes the perfomance of the assignee in the recent years. The overall statistics for this portfolio help to analyze the areas where the assignee is performing well. The filing trend, perfomance across the tech centers and the perfomance of the recent applications has been mentioned below. All the stats are calculated based on the perfomance in USPTO.

How does the overall patent portfolio of Advanced Micro Devices, Inc. look like?

Assignee Art Units
Total Applications: 11,932 1,785,629
Granted Patents: 10,348 1,170,811
Grant Index 90.63% ↑ 82.06%
Abandoned/Rejected Applications: 1,070 (9.37%) 256,023 (17.94%)
In-Process Applications: 509 358,795
Average Grant Time: 2.78 Years ↑ 2.64 Years
Average Office Actions: 1.63 ↑ 1.49

Which Technology Area Advanced Micro Devices, Inc. is filing most patents in? (Last 10 years)

Art Unit Definition Total Applications
2818 Semiconductors/Memory 688
2812 Semiconductors/Memory 648
2813 Semiconductors/Memory 534
2823 Semiconductors/Memory 397
2814 Semiconductors/Memory 350

How many patents are Advanced Micro Devices, Inc. filing every year?

Year Total Applications Predicted
2022 0* 837
2021 35* 794
2020 188 704
2019 250 250
2018 234 –
2017 236 –
2016 221 –
2015 128 –
2014 156 –
2013 201 –

*The drop in the number of applications filed in last two years compared to previous years is because applications can take up to 18 months to get published

Recently filed patent applications of Advanced Micro Devices, Inc. in USPTO?

Publication number: US20220091921A1
Application number: 17/544,074

Abstract:
A data processor includes provides memory commands to a memory channel according to predetermined criteria. The data processor includes a first error code generation circuit, a second error code generation circuit, and a queue. The first error code generation circuit generates a first type of error code in response to data of a write request. The second error code generation circuit generates a second type of error code for the write request, the second type of error code different from the first type of error code. The queue is coupled to the first error code generation circuit and to the second error code generation circuit, for provides write commands to an interface, the write commands including the data, the first type of error code, and the second type of error code.

Publication date: 2022-03-24
Applicant: Advanced Micro Devices, Inc.
Inventors: James Magro R

Publication number: US20220092001A1
Application number: 17/543,136

Abstract:
Described is a method and apparatus for application migration between a dockable device and a docking station in a seamless manner. The dockable device includes a processor and the docking station includes a high-performance processor. The method includes determining a docking state of a dockable device while at least an application is running. Application migration from the dockable device to a docking station is initiated when the dockable device is moving to a docked state. Application migration from the docking station to the dockable device is initiated when the dockable device is moving to an undocked state. The application continues to run during the application migration from the dockable device to the docking station or during the application migration from the docking station to the dockable device.

Publication date: 2022-03-24
Applicant: Advanced Micro Devices, Inc.
Inventors: Campbell Jonathan Lawrence

Publication number: US20220171717A1
Application number: 17/539,367

Abstract:
A system includes a memory implementing one or more virtual queues and a processor coupled to the memory. In response to issuing one or more requests for data, a processor maps one or more of the requests for data to a return queue structure. The processor then allocates one or more virtual queues to the return queue structure based on the mapped requests. In response to allocating the virtual queues to the return queue, the processor writes the data indicated in the mapped requests to the allotted virtual queues and enables the return queue for arbitration. When the return queue is enabled for arbitration, the processor reads out the data written to the allocated virtual queues, processes the read out data, and provides the processed data to a processing pipeline.

Publication date: 2022-06-02
Applicant: Advanced Micro Devices, Inc.
Inventors: Fataneh Ghodrat

How are Advanced Micro Devices, Inc.’s applications performing in USPTO?

Application Number Title Status Art Unit Examiner
17/544,074 Data Integrity For Persistent Memory Systems And The Like Docketed New Case – Ready for Examination OPAP Central, Docket
17/543,136 System And Method For Application Migration For A Dockable Device Docketed New Case – Ready for Examination OPAP Central, Docket
17/539,367 Adaptive Out Of Order Arbitration For Numerous Virtual Queues – OPAP Central, Docket
17/533,548 Dynamic Voltage Frequency Scaling Based On Active Memory Barriers Docketed New Case – Ready for Examination OPAP Central, Docket
17/532,469 Performing Scan Data Transfer Inside Multi-Die Package With Serdes Functionality Docketed New Case – Ready for Examination OPAP Central, Docket