Fuji Electric Co., Ltd`s Profile
This article summarizes the perfomance of the assignee in the recent years. The overall statistics for this portfolio help to analyze the areas where the assignee is performing well. The filing trend, perfomance across the tech centers and the perfomance of the recent applications has been mentioned below. All the stats are calculated based on the perfomance in USPTO.
How does the overall patent portfolio of Fuji Electric Co., Ltd look like?
| Total Applications: | 35 |
| Granted Patents: | 29 |
| Grant Index | 82.86 % |
| Abandoned/Rejected Applications: | 6 (17.14%) |
| In-Process Applications: | 0 |
| Average Grant Time: | 2.21 Years |
| Average Office Actions: | 1.34 |
Which Technology Area Fuji Electric Co., Ltd is filing most patents in? (Last 10 years)
| Art Unit | Definition | Total Applications |
| 2814 | Semiconductors/Memory | 5 |
| 2811 | Semiconductors/Memory | 2 |
| 2815 | Semiconductors/Memory | 2 |
| 2823 | Semiconductors/Memory | 2 |
| 2891 | Semiconductors/Memory | 2 |
How many patents are Fuji Electric Co., Ltd filing every year?
| Year | Total Applications |
| 2022 | 0* |
| 2021 | 0* |
| 2020 | 0 |
| 2019 | 0 |
| 2018 | 0 |
*The drop in the number of applications filed in last two years compared to previous years is because applications can take up to 18 months to get published
Recently filed patent applications of Fuji Electric Co., Ltd in USPTO?
Publication number: US20180315842A1
Abstract:
The SiC-IGBT includes a p-type collector layer, an n−-type voltage-blocking-layer provided on the collector layer, p-type base regions provided on the n−-type voltage-blocking-layer, n+-type emitter regions provided in an upper portion of the p-type base region, a gate insulating film provided in an upper portion of the voltage-blocking-layer, and a gate electrode provided on the gate insulating film. The p-type buffer layer has thickness of five micrometers or more and 20 micrometers or less and is doped with Al at impurity concentration of 5×1017 cm−3 or more and 5×1018 cm−3 or less and doped with B at impurity concentration of 2×1016 cm−3 or more and less than 5×1017 cm−3.
Publication date: 2018-11-01
Applicant: Fuji Electric Co., Ltd
Inventors: Tawara Takeshi
Abstract:
Publication date: 2018-11-01
Applicant: Fuji Electric Co., Ltd
Inventors: Tawara Takeshi
How are Fuji Electric Co., Ltd’s applications performing in USPTO?
| Application Number | Title | Status | Art Unit | Examiner |
| 15963698 | Silicon Carbide Epitaxial Wafer, Silicon Carbide Insulated Gate Bipolar Transistor, And Method Of Manufacturing The Same | Patented Case | 2895 | Naraghi, Ali |
