Cypress Semiconductor Corporation Patent Portfolio Statistics

tip_user1

Cypress Semiconductor Corporation

Profile Summary

This article summarizes the perfomance of the assignee in the recent years. The overall statistics for this portfolio help to analyze the areas where the assignee is performing well. The filing trend, perfomance across the tech centers and the perfomance of the recent applications has been mentioned below. All the stats are calculated based on the perfomance in USPTO.

How does the overall patent portfolio of Cypress Semiconductor Corporation look like?

Assignee Art Units
Total Applications: 6,901 1,921,652
Granted Patents: 6,025 1,279,417
Grant Index 94.78% ↑ 82.23%
Abandoned/Rejected Applications: 332 (5.22%) 276,556 (17.77%)
In-Process Applications: 542 365,679
Average Grant Time: 2.83 Years ↑ 2.63 Years
Average Office Actions: 2.02 ↑ 1.47

Which Technology Area Cypress Semiconductor Corporation is filing most patents in? (Last 10 years)

Art Unit Definition Total Applications
2818 Semiconductors/Memory 589
2824 Semiconductors/Memory 464
2816 Semiconductors/Memory 367
2827 Semiconductors/Memory 367
2819 Semiconductors/Memory 201

How many patents are Cypress Semiconductor Corporation filing every year?

Year Total Applications Predicted
2022 0* 408
2021 14* 330
2020 75 384
2019 112 112
2018 108 –
2017 97 –
2016 88 –
2015 123 –
2014 164 –
2013 211 –

*The drop in the number of applications filed in last two years compared to previous years is because applications can take up to 18 months to get published

Recently filed patent applications of Cypress Semiconductor Corporation in USPTO?

Publication number: US20140264552A1
Application number: 13/795,036

Abstract:
A memory cell can include at least a first programmable section coupled between a supply node and a first data node; a volatile storage circuit coupled to the first data node; and the programmable section includes a programmable transistor having a first source/drain (S/D) region shared with a first transistor, and a second S/D region shared with a second transistor; wherein the first S/D region has a different dopant diffusion profile than the second S/D region, and the programmable transistor has a charge storage structure formed between its control gate and its channel. Methods of forming such a memory cell are also disclosed.

Publication date: 2014-09-18
Applicant: Cypress Semiconductor Corporation
Inventors: Kaveh Shakeri

Publication number: US20140219018A1
Application number: 13/761,217

Abstract:
A non-volatile memory device comprising a memory cell array including memory cells distributed among a plurality of sectors; a controller operable to program, read, and erase memory cells in said memory array, said controller further operable to generate and store EPLI values for programming a number of EPLI bits in one of said plurality of sectors with said stored EPLI values; and a comparator to compare said stored EPLI values with EPLI values programmed in said EPLI bits.

Publication date: 2014-08-07
Applicant: Cypress Semiconductor Corporation
Inventors: Ifat Kalderon Nitzan

How are Cypress Semiconductor Corporation’s applications performing in USPTO?

Application Number Title Status Art Unit Examiner
13/795,036 Nonvolatile Memory Cells And Methods Of Making Such Cells Patented Case 2827 Ho, Hoai V
13/761,217 Non-Volatile Memory Device With An Epli Comparator Patented Case 2131 Elmore, Reba I