Toshiba Memory Corporation Patent Portfolio Statistics

tip_user1

Toshiba Memory Corporation

Profile Summary

This article summarizes the perfomance of the assignee in the recent years. The overall statistics for this portfolio help to analyze the areas where the assignee is performing well. The filing trend, perfomance across the tech centers and the perfomance of the recent applications has been mentioned below. All the stats are calculated based on the perfomance in USPTO.

How does the overall patent portfolio of Toshiba Memory Corporation look like?

Assignee Art Units
Total Applications: 8,790 1,962,238
Granted Patents: 8,327 1,285,130
Grant Index 96.14% ↑ 81.12%
Abandoned/Rejected Applications: 334 (3.86%) 299,200 (18.88%)
In-Process Applications: 129 377,908
Average Grant Time: 2.11 Years ↓ 2.52 Years
Average Office Actions: 1.12 ↓ 1.44

Which Technology Area Toshiba Memory Corporation is filing most patents in? (Last 10 years)

Art Unit Definition Total Applications
2827 Semiconductors/Memory 1,207
2824 Semiconductors/Memory 1,078
2818 Semiconductors/Memory 401
2825 Semiconductors/Memory 385
2814 Semiconductors/Memory 216

How many patents are Toshiba Memory Corporation filing every year?

Year Total Applications Predicted
2022 0* 1023
2021 19* 1037
2020 60 1010
2019 735 735
2018 722 –
2017 673 –
2016 904 –
2015 736 –
2014 579 –
2013 591 –

*The drop in the number of applications filed in last two years compared to previous years is because applications can take up to 18 months to get published

Recently filed patent applications of Toshiba Memory Corporation in USPTO?

Publication number: US20220083278A1
Application number: 17/536,502

Abstract:
According to one embodiment, a storage system performs a first allocation operation of allocating, for a first namespace, a plurality of first blocks included in the blocks of a nonvolatile memory. The storage system performs a read operation, a write operation or an erase operation on one of the first blocks in response to a command received from a host to read, write or erase the one first block, counts the total number of erase operations performed on the first blocks, and notifies the host of the counted number of erase operations in response to a command received from the host to obtain an erase count associated with the first namespace.

Publication date: 2022-03-17
Applicant: Toshiba Memory Corporation
Inventors: Kanno Shinichi

Publication number: US20220083497A1
Application number: 17/537,126

Abstract:
A system for reading stored data may include one or more Ethernet drives and a controller, both configured to communicatively connect to a host device. The controller may receive a first read command from the host device, determine a first drive among the one or more Ethernet drives using the first read command and a mapping table, translate the first read command into a second read command, and send the second read command to the first drive. Responsive to receiving the second read command, the first drive may send a first remote data transfer instruction to the host device independent of the controller. The first remote data transfer instruction may include stored data read from the first drive to cause the host device to write the stored data read from the first drive to one or more memory buffers in the host device indicated by the second read command.

Publication date: 2022-03-17
Applicant: Toshiba Memory Corporation
Inventors: Klein Yaron

Publication number: US20220084846A1
Application number: 17/532,074

Abstract:
A semiconductor manufacturing apparatus includes a mounting unit arranged to mount an annular member, having an annular shape, to a work substrate including a first substrate and a second substrate bonded to each other so that the annular member surrounds the first substrate. The apparatus further includes a holding unit arranged to hold the work substrate having the annular member mounted thereto. The apparatus further includes a first fluid supply unit arranged to supply a first fluid to the second substrate of the work substrate held by the holding unit.

Publication date: 2022-03-17
Applicant: Toshiba Memory Corporation
Inventors: Hayashi Hidekazu

How are Toshiba Memory Corporation’s applications performing in USPTO?

Application Number Title Status Art Unit Examiner
17/536,502 Storage System, Information Processing System And Method For Controlling Nonvolatile Memory Docketed New Case – Ready for Examination OPAP Central, Docket
17/537,126 System And Method For Storing Data Using Ethernet Drives And Ethernet Open-Channel Drives Docketed New Case – Ready for Examination 2454 Lee, Philip C
17/532,074 Semiconductor Manufacturing Apparatus And Method For Manufacturing Semiconductor Device Docketed New Case – Ready for Examination OPAP Central, Docket
17/530,748 Memory System And Control Method Docketed New Case – Ready for Examination OPAP Central, Docket
17/526,971 Selective Erasure Of Data In A Ssd Docketed New Case – Ready for Examination OPAP Central, Docket