Renesas Electronics Corporation Patent Portfolio Statistics

Renesas Electronics Corporation

Profile Summary

This article summarizes the perfomance of the assignee in the recent years. The overall statistics for this portfolio help to analyze the areas where the assignee is performing well. The filing trend, perfomance across the tech centers and the perfomance of the recent applications has been mentioned below. All the stats are calculated based on the perfomance in USPTO.

How does the overall patent portfolio of Renesas Electronics Corporation look like?

Assignee Art Units
Total Applications: 18,416 2,119,902
Granted Patents: 16,344 1,433,486
Grant Index 89.68% 82.09%
Abandoned/Rejected Applications: 1,880 (10.32%) 312,741 (17.91%)
In-Process Applications: 184 373,675
Average Grant Time: 2.32 Years 2.55 Years
Average Office Actions: 1.21 1.43

Which Technology Area Renesas Electronics Corporation is filing most patents in? (Last 10 years)

Art Unit Definition Total Applications
2818 Semiconductors/Memory 1,329
2816 Semiconductors/Memory 884
2824 Semiconductors/Memory 878
2827 Semiconductors/Memory 715
2814 Semiconductors/Memory 664

How many patents are Renesas Electronics Corporation filing every year?

Year Total Applications Predicted
2022 0* 956
2021 66* 934
2020 169 820
2019 248 248
2018 346
2017 560
2016 576
2015 639
2014 610
2013 667

*The drop in the number of applications filed in last two years compared to previous years is because applications can take up to 18 months to get published

Recently filed patent applications of Renesas Electronics Corporation in USPTO?

Publication number: US20220166443A1
Application number: 17/529,885

Abstract:
A semiconductor device performs sequential comparison of an analog input signal and a reference voltage to digitally convert the analog input signal. The semiconductor device includes an upper DAC generating a high-voltage region of the reference voltage based on a predetermined code, a lower DAC generating a low-voltage region of the reference voltage based on the code, and an injection DAC having the same configuration as that of the lower DAC and adjusting the low-voltage region of the reference voltage.

Publication date: 2022-05-26
Applicant: Renesas Electronics Corporation
Inventors: Ebata Tomohiko


Publication number: US20220077191A1
Application number: 17/528,585

Abstract:
To provide a semiconductor device having a thin-film BOX-SOI structure and capable of realizing a high-speed operation of a logic circuit and a stable operation of a memory circuit. A semiconductor device according to the present invention includes a semiconductor support substrate, an insulation layer having a thickness of at mast 10 nm, and a semiconductor layer. In an upper surface of the semiconductor layer, a first field-effect transistor including a first gate electrode and constituting a logic circuit is formed. Further, in the upper surface of the semiconductor layer, a second field-effect transistor including a second gate electrode and constituting a memory circuit is formed. At least three well regions having different conductivity types are formed in the semiconductor support substrate. In the presence of the well regions, a region of the semiconductor support substrate below the first gate electrode and a region of the semiconductor support substrate below the second gate electrode are electrically separated from each other.

Publication date: 2022-03-10
Applicant: Renesas Electronics Corporation
Inventors: Iwamatsu Toshiaki


Publication number: US20220149206A1
Application number: 17/521,041

Abstract:
A semiconductor device includes a ferroelectric memory having a ferroelectric film between a gate electrode and a semiconductor substrate. The ferroelectric film and a metal film are not formed just above an element isolation region formed in a trench in an upper surface of the semiconductor substrate, but are formed on the semiconductor substrate in the active region defined by the element isolation region to prevent a state in which a polarization state in the ferroelectric film of the active region and a polarization state in the ferroelectric film on the element isolation region differ from each other.

Publication date: 2022-05-12
Applicant: Renesas Electronics Corporation
Inventors: Maruyama Takahiro


How are Renesas Electronics Corporation’s applications performing in USPTO?

Application Number Title Status Art Unit Examiner
17/529,885 Semiconductor Device OPAP Central, Docket
17/528,585 Semiconductor Device And Method For Controlling Semiconductor Device Docketed New Case – Ready for Examination OPAP Central, Docket
17/521,041 Semiconductor Device And Method Of Manufacturing The Same Docketed New Case – Ready for Examination OPAP Central, Docket
17/520,461 Semiconductor Device And Method Of Manufacturing The Same OPAP Central, Docket
17/520,020 Semiconductor Device OPAP Central, Docket