Globalfoundries Inc Patent Portfolio Statistics

Publication number: US20220108950A1
Application number: 17/553,924

Abstract:
An integrated circuit product includes a first layer of insulating material including a first insulating material. The first layer of insulating material is positioned above a device layer of a semiconductor substrate. The first layer of insulating material has a lowermost surface positioned above an uppermost surface of a gate of a transistor in a device layer of a semiconductor substrate. The device layer includes transistors. A metallization blocking structure is positioned in an opening in the first layer of insulating material. The metallization blocking structure has a lowermost surface above the uppermost surface of the gate and includes a second insulating material that is different from the first insulating material. The metallization blocking structure includes a second insulating material that is different from the first insulating material. A metallization trench is defined in the first layer of insulating material on opposite sides of the metallization blocking structure. A conductive metallization line includes first and second portions positioned in the metallization trench on opposite sides of the metallization blocking structure. The conductive metallization line has a long axis extending along the first and second portions.

Publication date: 2022-04-07
Applicant: Globalfoundries Inc.
Inventors: Ruilong Xie

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Publication number: US20220069125A1
Application number: 17/454,481

Abstract:
The present disclosure relates generally to semiconductor structures, and more particularly to asymmetric field effect transistors (FET) on fully depleted silicon on insulator (FDSOI) semiconductor devices for high frequency and high voltage applications and their method of manufacture. The semiconductor device of the present disclosure includes a semiconductor-on-insulator (SOI) layer disposed above a substrate, the SOI layer having a source region, a channel region, a drift region and a drain region, where the drift region adjoins the drain region and the channel region, a gate structure disposed on the channel region, a multilayer drain spacer disposed on a drain-facing sidewall of the gate structure and covering the drift region, and a source spacer disposed on a source-facing sidewall of the gate structure, where the source and drain spacers are asymmetric with each other.

Publication date: 2022-03-03
Applicant: Globalfoundries Inc.
Inventors: Cortes Ignasi

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Publication number: US20220057576A1
Application number: 17/454,063

Abstract:
The present disclosure generally relates to semiconductor devices for use in optoelectronic/photonic applications and integrated circuit (IC) chips. More particularly, the present disclosure relates to semiconductor devices having a reflector and a photonic component and a method of forming the same. The present disclosure provides a semiconductor device having a substrate, a photonic component arranged above the substrate, a bottom reflector arranged above the substrate and positioned below the photonic component, in which the bottom reflector has a plurality of grating structures configured to reflect electromagnetic waves towards the photonic component, and a top reflector arranged above the photonic component, in which the top reflector has a plurality of grating structures configured to reflect electromagnetic waves towards the photonic component.

Publication date: 2022-02-24
Applicant: Globalfoundries Inc.
Inventors: Bo Peng

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